3D Vertical Transistor Salicidation for Density Scaling

The patent transitions from 2D planar transistors to 3D vertical transistors by stacking multiple transistor layers vertically. This dimensional change allows continuous scaling of transistor density without proportionally increasing fabrication complexity, as the vertical stacking approach uses adapted versions of existing 2D fabrication processes rather than entirely new manufacturing methods.

The patent performs salicidation of source and drain regions before forming the isolation dielectric layer. This preliminary action ensures that the entire cross-sectional surface area of the vertical channels is salicided, including regions that would otherwise be inaccessible after isolation is formed. The salicidation process is completed while all surfaces are still accessible, maximizing the conductive surface area before the isolation structure is put in place.

The patent combines multiple salicidation operations into a single unified process step. By performing blanket salicidation across the entire wafer surface before isolation, all vertical channel surfaces are salicided simultaneously in one process operation. This merging of operations dramatically improves processing efficiency while maintaining precise control through the self-limited nature of the salicidation reaction and subsequent selective removal of excess salicide material.