Vertical Transistor with Segmented Active Layer
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Solution Overview
Problem
Transistors in electronic devices face challenges such as complex fabrication processes, degraded performance when simplifying processing, and limitations in reducing transistor area, which affect integration and resolution in display and lighting devices.
Innovation Solution
A transistor with a vertical structure is designed, featuring a gate electrode with a reverse tapered shape or stepped portions, an active layer with a short channel, and insulation patterns to reduce parasitic capacitance and contact resistance, allowing for superior process convenience and miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistor area is reduced to achieve high integration, then integration level is improved, but manufacturing precision and processing difficulty worsen
Solution Approach 1:
The patent transitions from a planar transistor structure to a vertical structure where the active layer extends in the vertical direction above the gate electrode. This dimensional change allows the transistor to achieve high integration with reduced area occupation while maintaining manufacturable dimensions and processing precision, as the vertical extension provides functional channel length without increasing lateral footprint
2Ease of manufacture
If fabrication process is simplified to improve ease of manufacture, then ease of manufacture is improved, but transistor performance deteriorates
Solution Approach 1:
The active layer is segmented into multiple portions (first portion above gate, second portion extending vertically, third portion on insulating film). This segmentation allows each portion to be optimized for specific functions while using standard deposition processes, achieving both ease of manufacture and high performance without requiring complex specialized fabrication steps
3Reliability
If contact resistance between source/drain electrode and active layer is reduced, then electrical conductivity is improved, but device complexity increases
Solution Approach 1:
The source/drain electrodes are positioned to overlap with the active layer portions before final insulation layer deposition. This preliminary positioning ensures optimal contact alignment and reduced contact resistance, while the subsequent insulation layer formation encapsulates this optimized contact structure without adding further complexity to the contact interface
4Reliability
If parasitic capacitance is reduced to improve transistor characteristics, then transistor performance is improved, but device complexity increases
Solution Approach 1:
An insulation pattern is strategically placed between the active layer and the second insulation layer in the vertical channel region. This extracted insulation layer removes the source of parasitic capacitance between these conductive elements, improving transistor characteristics while using a simple additive structure that does not significantly increase overall device complexity
Data Source
AI summary
An electronic device can include a panel; a driver circuit configured to drive the panel; and a transistor disposed in the panel, the transistor including: a gate electrode disposed on a substrate, a first insulating film disposed on the gate electrode, an active layer disposed on the first insulating film, the active layer including: a first portion of the active layer overlapping with an upper surface of the gate electrode, a second portion of the active layer extending from the first portion, being disposed along a side surface of the gate electrode and including a channel area, and a third portion of the active layer extending from the second portion of the active layer, the third portion of the active layer being disposed on a portion of the first insulating film that does not overlap with the gate electrode, a second insulating film disposed on the active layer, a first electrode disposed on the second insulating film, the first electrode being electrically connected to the first portion of the active layer, and a second electrode disposed on the second insulating film, the second electrode being electrically connected to the third portion of the active layer.