Vertical Transistor Fabrication via Selective Dielectric Isolation
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling integrated circuit devices to increase device density while maintaining efficient processing, particularly in the complex and costly fabrication of vertical transistors, which require improved methods for defining channel regions in vertical transistor devices.
Innovation Solution
A method involving a stacked structure of layers on a substrate, where selective dielectric formation on the sidewalls of specific layers electrically isolates source and drain regions from the gate contacting layer, allowing for self-alignment and simplifying the processing of vertical transistors, particularly beneficial for CMOS circuitry and SRAM cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical transistor devices are fabricated to increase device density, then device density is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The method performs preliminary actions by forming dielectric layers on sidewalls of source and drain regions before forming the gate contacting layer. This self-alignment approach pre-establishes the spatial relationships needed for subsequent processing steps, reducing the need for complex alignment procedures and multiple lithography steps that would otherwise be required to achieve precise vertical alignment of the gate with the channel region.
Solution Approach 2:
The dielectric layers formed on the sidewalls of the source and drain regions automatically serve as alignment references for the gate contacting layer formation. The self-alignment mechanism allows the structure itself to define the positioning of subsequent layers, eliminating the need for external alignment tools and complex processing procedures, thereby reducing manufacturing complexity while maintaining high device density.
2Area of moving object
If vertical transistor devices are fabricated to reduce layout area, then layout area is reduced, but processing complexity increases
Solution Approach 1:
The method performs preliminary actions by forming dielectric layers on sidewalls of source and drain regions before forming the gate contacting layer. This self-alignment approach pre-establishes the spatial relationships needed for subsequent processing steps, reducing the need for complex alignment procedures and multiple lithography steps that would otherwise be required to achieve precise vertical alignment of the gate with the channel region.
Solution Approach 2:
The dielectric layers formed on the sidewalls of the source and drain regions automatically serve as alignment references for the gate contacting layer formation. The self-alignment mechanism allows the structure itself to define the positioning of subsequent layers, eliminating the need for external alignment tools and complex processing procedures, thereby reducing manufacturing complexity while maintaining high device density.
3Manufacturing precision
If selective dielectric formation is used to achieve self-alignment, then manufacturing precision is improved, but process complexity increases
Solution Approach 1:
The dielectric layers formed on the sidewalls of the source and drain regions automatically serve as alignment references for the gate contacting layer formation. The self-alignment mechanism allows the structure itself to define the positioning of subsequent layers, eliminating the need for external alignment tools and complex processing procedures, thereby reducing manufacturing complexity while maintaining high device density.
Solution Approach 2:
The method merges multiple functions into a single integrated process: the dielectric layers simultaneously provide electrical isolation of the source and drain regions from the gate contacting layer and serve as self-alignment references for precise gate positioning. This consolidation of isolation and alignment functions into a single structural element reduces the number of separate processing steps required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables efficient alignment and isolation of channel regions in vertical transistors, facilitating denser device integration and reducing processing complexity, thereby enhancing the scalability and cost-effectiveness of vertical transistor fabrication.
Implementation Method 1
selectively forming a dielectric on the sidewalls of the first and third layers of the fin
Data Source
AI summary
The disclosed technology generally relates semiconductor devices and more particularly to a vertical transistor device, and a method of fabricating the same. In one aspect, the method includes providing, on a substrate, a fin formed of a stack of a first layer, a second layer and a third layer, wherein the second layer is positioned above the first layer and the third layer is positioned above the second layer. The method additionally includes forming a dielectric on the sidewalls of the first and third layers of the fin selectively against a sidewall of the second layer, and the method additionally includes forming a gate contacting layer for contacting a sidewall of the second layer. The first and third layers define a source region and a drain region, respectively, of the vertical transistor device. The second layer defines a channel region of the vertical transistor device. The dielectric on the sidewalls of the first and third layers electrically isolates the source and drain regions from the gate contacting layer.