3D Vertical Transistor Fabrication via Selective Dielectric Etching
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Solution Overview
Problem
Current semiconductor fabrication techniques face challenges in scaling transistors to single-digit nanometer nodes, limiting the density of 2D circuits, and there is a need for 3D integration of logic chips to overcome these limitations by stacking transistors vertically.
Innovation Solution
The method involves forming a stack of dielectric layers with selective etch properties, epitaxially growing channel material to create vertical channels, and forming gate structures on these channels, allowing for current flow perpendicular to the wafer surface, which enables the creation of 3D CMOS devices with enhanced density and layout options without the need for oxide isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 2D planar transistors are used to increase transistor density, then scaling efforts have greatly increased the number of transistors per unit area, but scaling efforts are running into greater challenges as scaling enters single digit nanometer semiconductor device fabrication nodes
Solution Approach 1:
The patent transitions from 2D planar transistors to 3D vertical transistors by stacking multiple transistor layers vertically. This dimensional change allows continued increase in transistor density without further scaling of individual transistor dimensions, thereby avoiding the manufacturing precision challenges at single digit nanometer nodes while maintaining scaling benefits
2Quantity of substance
If 3D integration is implemented for logic chips, then transistor density in volume is increased, but application to random logic designs is substantially more difficult
Solution Approach 1:
The patent segments the 3D integration process into standardized layers including alternating dielectric layers and semiconductor layers with vertical channels. This segmentation creates modular building blocks that can be systematically assembled, reducing the overall complexity of 3D integration for logic chip designs
Solution Approach 2:
The patent changes key parameters including using selective dielectric materials with different etch rates, controlling epitaxial growth conditions for vertical channels, and adjusting layer thicknesses to optimize device performance. These parameter changes enable precise control over the 3D structure formation, making the integration process more manageable
3Manufacturing precision
If vertical channels are formed with epitaxial growth, then precise alignment with gate electrodes is achieved, but selective removal of intermediate dielectric layers is required
Solution Approach 1:
The patent introduces intermediate dielectric layers as sacrificial materials during the fabrication process. These intermediary layers are selectively removed after serving their purpose of defining and protecting vertical channel regions, enabling precise gate electrode alignment while the removed materials simplify the overall structure
4Ease of manufacture
If oxide isolation is eliminated from 3D nano stack, then manufacturing process is simplified, but new isolation methods must be implemented
Solution Approach 1:
The patent employs dielectric layers that are selectively removed (discarded) after serving their structural and protective functions during fabrication. This approach eliminates the need for permanent oxide isolation structures while the selective removal process itself becomes part of the simplified manufacturing flow
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for higher density circuits with reduced costs, precise alignment of gate electrodes, and increased circuit density through 360-degree access to channel, source, and drain regions, facilitating more efficient 3D device architecture.
Implementation Method 1
epitaxially growing channel material within uncovered openings to form vertical channels
Data Source
AI summary
Aspects of the present disclosure provide a vertical channel 3D semiconductor device sand a method for fabricating the same. The 3D semiconductor devices may have vertical channels of the same or different epitaxially grown doped materials. Sidewall structures are formed around each vertical channel by masking and etching material between the vertical channels. A dielectric layer in each of the sidewalls is etched down to the vertical channel and a gate electrode structure is formed in the opening. The gate electrode structure may include an interfacial oxide, a high-K layer and alternating metal layers. Local interconnects connect to the metal of the gate structure.