Vertical Transistor Self-Aligned Gate Structure
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Solution Overview
Problem
Current transistor technologies face challenges in scaling beyond the 7 nanometer node without relying on gate mask cut processes in tight pitch structures, and they suffer from variability in gate metal foot at the bottom of vertical fins, leading to increased electrical resistance.
Innovation Solution
The method involves forming vertical fins with a self-aligned gate structure that includes a gate dielectric layer, a work function layer, and a gate metal layer, where the gate metal layer fills the gap between adjacent fin sidewalls, and a bi-material top spacer layer with two dielectric materials, allowing for reduced electrical resistance and controlled gate structure foot size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional gate structures are used in tight pitch structures, then manufacturing process complexity increases due to gate mask cut processes, but device scaling is limited
Solution Approach 1:
The gate structure is self-aligned to the vertical fins through the formation of spacer layers on the fin sidewalls. The spacer layers automatically define the gate position relative to the fins, eliminating the need for separate gate mask alignment processes and enabling self-aligned fabrication that reduces process complexity while maintaining precision
Solution Approach 2:
The spacer layers are formed on the vertical fin sidewalls before the gate electrode is deposited. This preliminary formation of spacers pre-defines the gate boundaries and positions, allowing the gate to be self-aligned to the fins without requiring subsequent mask alignment steps
2Reliability
If gate metal foot size is reduced at the bottom of vertical fins, then electrical resistance increases, but device scaling is hindered
Solution Approach 1:
The gate structure incorporates a work function layer with specific material composition and thickness tailored to the local region at the bottom of the vertical fins. This local optimization of the gate structure ensures adequate electrical contact and reduced resistance at the critical fin-bottom interface, while allowing the rest of the gate to be scaled down
Data Source
AI summary
A method of forming a vertical transistor is provided. The method includes forming a first set of vertical fins in a first row on a first bottom source/drain layer, and a second set of vertical fins in a second row on a second bottom source/drain layer, wherein the vertical fins in the same row are separated by a spacing with a sidewall-to-sidewall distance, SD, and the vertical fins in the same column of adjacent rows are separated by a gap having a gap distance, GD. The method further includes forming a gate metal layer on the first set of vertical fins and the second set of vertical fins, wherein the gate metal layer does not fill in the gap between vertical fins in the same column, and forming a cover layer plug in the remaining gap after forming the gate metal layer.