Vertical Transistor Pillar Layout for Series Connection Without Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices with vertical transistors require additional device isolation regions and complex wiring to connect transistors in series, leading to increased area usage and potential short circuits between transistors.
Innovation Solution
The semiconductor device configuration includes silicon pillars with gate electrodes on multiple sides and conductive layers on top, eliminating the need for device isolation regions and allowing transistors to be connected in series without additional isolation, thereby reducing area usage and preventing short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If device isolation regions are used to separate active regions containing vertical transistors, then short circuits between transistors are prevented, but the device area increases and manufacturing complexity increases
Solution Approach 1:
The patent removes the device isolation region from the semiconductor structure, extracting the problematic element that caused area increase and manufacturing complexity while maintaining transistor separation through the inherent vertical pillar geometry and selective etching processes
Solution Approach 2:
The vertical transistor pillars inherently provide their own isolation through their three-dimensional structure and the selective formation of gate electrodes on specific side faces, eliminating the need for external device isolation regions to prevent short circuits
2Ease of manufacture
If device isolation regions and additional wiring are added to connect transistors in series, then transistor connection is achieved, but the device area increases
Solution Approach 1:
The patent merges the transistor connection function directly into the vertical pillar structure by forming conductive layers on the top surfaces of adjacent pillars and creating shared gate electrode structures, eliminating the need for separate wiring layers and isolation regions
Solution Approach 2:
The patent transitions from planar two-dimensional transistor connections to three-dimensional vertical connections by utilizing the height dimension of the vertical pillars, allowing series connection through vertical stacking and top-surface contact rather than lateral wiring
3Area of stationary object
If vertical transistors are used instead of planar transistors, then area efficiency is improved, but device isolation regions are still required increasing complexity
Solution Approach 1:
The patent extracts and removes the device isolation region that was traditionally required with vertical transistors, simplifying the overall device structure while maintaining the area efficiency benefits of vertical transistor architecture
Solution Approach 2:
The vertical transistor structure provides inherent isolation through its three-dimensional pillar geometry and selective gate electrode formation, making the structure self-isolating and eliminating the need for additional device isolation regions
Data Source
AI summary
A semiconductor device includes an active region which is surrounded by a device isolation region on a semiconductor substrate and which extends in a first direction; a silicon pillar which separates the active region along the first direction into a first lower diffusion layer and a second lower diffusion layer; a first gate electrode covering a first side face of the silicon pillar which is located on a side of the first lower diffusion layer; a second gate electrode covering a second side face of the silicon pillar which is located on a side of the second lower diffusion layer; a conductive layer provided on a top face of the silicon pillar; and a device isolation insulating film contacting with a third side face of the silicon pillar which is different from the first side face and the second side face.