Array of vertical transistors having channel regions connected by an elongated conductor line
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Solution Overview
Problem
Current methods for forming arrays of vertical transistors in memory or integrated circuitry face challenges in efficiently creating structures that allow for reliable non-volatile data storage, particularly with ferroelectric capacitors where reading memory states can reverse the polarization, necessitating immediate rewriting.
Innovation Solution
The method involves forming laterally-spaced and horizontally-elongated transistor-material lines with a horizontally-elongated conductor line between them, cutting these lines to form spaced pillars, and creating a conductive gate line that interconnects multiple vertical transistors, using insulative and conductive materials to ensure direct electrical coupling and programmable charge storage, potentially incorporating ferroelectric materials for non-volatile memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ferroelectric capacitors are used for non-volatile memory storage, then data retention capability is improved, but reading memory states causes polarization reversal requiring immediate rewriting
Solution Approach 1:
The patent divides the memory cell structure into distinct vertical components including separate source/drain regions, channel regions, and gate structures. This segmentation allows for optimized control of each region, enabling better management of the ferroelectric capacitor's polarization state and reducing unwanted polarization reversal during read operations.
Solution Approach 2:
The patent transitions from planar transistor structures to vertical transistor architectures, stacking multiple functional layers vertically. This dimensional change increases the effective storage capacity and allows for more efficient memory cell designs that can maintain ferroelectric polarization states without requiring immediate rewriting after reads.
2Reliability
If vertical transistor structures are formed with multiple processing steps, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent combines multiple processing operations into integrated steps. For example, the formation of insulative material layers and conductive gate structures is merged with the transistor fabrication process, reducing the total number of discrete manufacturing steps while maintaining vertical transistor performance.
Solution Approach 2:
The patent employs universal processing techniques that can form multiple structures simultaneously. The same deposition and etching processes used for transistor gates are also used to form conductive lines and interconnect structures, simplifying the overall manufacturing process despite the vertical architecture's complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of arrays of vertical transistors with improved non-volatile data storage capabilities, reducing the need for immediate rewriting after reading and enhancing the reliability of memory cells by maintaining programmable states effectively.
Implementation Method 1
The gate insulator may be capable of being programmed between at least two retentive capacitive states whereby the transistor is non-volatile
Implementation Method 2
One type of non-volatile capacitor is a ferroelectric capacitor which has ferroelectric material as at least part of the insulating material. Ferroelectric materials are characterized by having two stable polarized states
Implementation Method 3
conductor material that directly electrically couples the conductor line to the channel regions of the transistor-material lines
Data Source
AI summary
An array of vertical transistors comprises spaced pillars individually comprising a channel region of individual vertical transistors. A horizontally-elongated conductor line directly electrically couples together individual of the channel regions of the pillars of a plurality of the vertical transistors. An upper source/drain region is above the individual channel regions of the pillars, a lower source/drain region is below the individual channel regions of the pillars, and a conductive gate line is operatively aside the individual channel regions of the pillars and that interconnects multiple of the vertical transistors. Methods are disclosed.