Vertical Transistor Shield Lines Reduce Bit Line Capacitance
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Solution Overview
Problem
As integrated circuit devices become more highly integrated, reducing the gate and channel lengths of transistors leads to increased capacitance between buried bit lines, which can hinder operating speed and performance.
Innovation Solution
The implementation of vertical channel transistors with buried bit lines and shield lines, where shield lines are strategically placed between bit lines to reduce capacitance through insulation layers or air gaps, thereby enhancing operational characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate length and channel length of transistors are reduced to increase integration density, then the degree of integration increases, but the capacitance between buried bit lines increases
Solution Approach 1:
The patent introduces shield lines as intermediary conductive structures positioned between adjacent buried bit lines. These shield lines act as mediators that electrically shield the bit lines from each other, reducing the capacitive coupling and electrical interference between them while allowing the bit lines to maintain their close spacing for high integration density
Solution Approach 2:
The patent extracts the shielding function from the bit line structure itself by introducing separate, dedicated shield lines. This allows the bit lines to focus on their primary function of data transmission while the shield lines handle the electromagnetic shielding, thereby reducing capacitance without compromising integration density
2Object-affected harmful factors
If shield lines are added between bit lines to reduce capacitance, then the capacitance between bit lines decreases, but the device complexity increases
Solution Approach 1:
The patent merges the formation of shield lines with existing fabrication processes by integrating them into the bit line formation sequence. The shield lines are formed using the same trenches and insulating layer processes as the bit lines, thereby reducing overall process complexity despite adding functional elements
Solution Approach 2:
The shield lines serve multiple functions: they reduce capacitance between bit lines, provide electromagnetic shielding, and can potentially serve as additional interconnect layers. This multi-functionality justifies the added structural complexity by delivering multiple benefits from a single structural addition
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively decreases capacitance between buried bit lines, increasing the operating speed and improving the performance of semiconductor devices by minimizing electrical interference.
Implementation Method 1
reduces a capacitance between the buried bit lines
Data Source
AI summary
An integrated circuit device includes a plurality of pillars protruding from a substrate in a first direction. Each of the pillars includes source/drain regions in opposite ends thereof and a channel region extending between the source/drain regions. A plurality of conductive bit lines extends on the substrate adjacent the pillars in a second direction substantially perpendicular to the first direction. A plurality of conductive shield lines extends on the substrate in the second direction such that each of the shield lines extends between adjacent ones of the bit lines. Related fabrication methods are also discussed.