Vertical Transistor Shielding Layer for Parasitic Capacitance Reduction
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Solution Overview
Problem
The reduction in transistor dimensions in semiconductor devices leads to short channel effects and increased leakage current, which are exacerbated by the adoption of vertical transistor structures, causing serious coupling effects and parasitic capacitance issues.
Innovation Solution
A method is introduced to fabricate semiconductor devices by forming a substrate with pillars and trenches, where a conductive shielding layer is created between adjacent doped regions to reduce coupling effects, using ion implantation and epitaxial silicon growth to separate and electrically connect the shielding layer to the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the dimension of the transistor is reduced to accelerate operating speed and meet miniaturization demands, then the operating speed and integration level are improved, but the channel length decreases leading to short channel effect and increased leakage current
Solution Approach 1:
The substrate is divided into multiple isolated regions by removing doped regions between adjacent pillars, creating separate doped regions below each pillar. This segmentation prevents the coupling effect between adjacent conductive regions and reduces parasitic capacitance, allowing transistor dimension reduction without excessive leakage current.
Solution Approach 2:
The invention transitions from a planar horizontal transistor structure to a vertical transistor structure where the channel extends in the vertical dimension through deep trenches. This dimensional change allows the channel length to be maintained or increased even as the planar footprint is reduced, mitigating short channel effects while enabling miniaturization.
2Productivity
If a vertical transistor structure is adopted to resolve short channel effect and enhance integration level, then the operating speed and integration level are improved, but the coupling effect between adjacent conductive regions becomes serious and parasitic capacitance increases
Solution Approach 1:
The harmful doped regions that cause coupling effects and parasitic capacitance between adjacent pillars are selectively removed (taken out) from the substrate. By etching away the doped regions in the spaces between pillars, the invention eliminates the source of parasitic capacitance while preserving the vertical transistor structure for high integration.
Solution Approach 2:
The invention introduces an intermediate structure (the removed doped regions or voids between pillars) that acts as a mediator to isolate adjacent conductive regions. This intermediate space prevents direct coupling between doped regions of neighboring vertical transistors, reducing parasitic capacitance while maintaining high integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance and enhances the operating speed and integration level of integrated circuits by isolating adjacent conductive regions, thereby improving device reliability.
Implementation Method 1
An ion implantation process is performed to implant dopants into the bottom of each trench
Implementation Method 2
A drive-in process is performed such that the dopants diffuse to a region below each pillar to form the doped region
Implementation Method 3
The conductive material includes doped epitaxial silicon
Data Source
AI summary
Provided is a method for fabricating a semiconductor device, including the following steps. A substrate having a plurality of pillars is provided, wherein a plurality of trenches are formed around each pillar. A doped region is formed in the substrate and below each pillar. The doped region below each trench is removed to form an opening such that the doped regions below the adjacent pillars are separated from each other. A shielding layer is formed in each opening.