Low Thermal Budget Source Drain Formation for Vertical Transistors
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Solution Overview
Problem
Conventional semiconductor manufacturing processes face challenges in forming top source/drain regions for vertical transistors due to high temperature requirements, which are detrimental to gate stacks and result in slow epitaxial growth rates and high costs, while low-temperature processes struggle with effective dopant incorporation and contact resistance.
Innovation Solution
A method involving the deposition of amorphous semiconductor material at low substrate temperatures followed by rapid annealing, such as millisecond or nanosecond laser annealing, to form doped polycrystalline source and drain regions with a planar surface, allowing for efficient dopant incorporation and reduced thermal budget to preserve gate stack integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional high temperature epitaxial processes are used to form top source/drain regions, then dopant incorporation is effective and contact resistance is reduced, but gate stack integrity is compromised and processing costs increase
Solution Approach 1:
The patent changes the temperature parameter from conventional high temperature (above 700°C) to low temperature (below 700°C, specifically 400-650°C range), enabling dopant incorporation and crystallization without compromising gate stack integrity. This parameter change resolves the contradiction by achieving effective dopant activation at lower temperatures through extended processing time and controlled atmosphere.
Solution Approach 2:
The patent applies preliminary doping to the amorphous semiconductor material before deposition, incorporating dopants into the amorphous phase. This preliminary action enables subsequent low-temperature crystallization to activate the dopants without requiring high-temperature processing, thus preserving gate stack integrity while ensuring effective dopant incorporation.
2Temperature
If low temperature processes are used to preserve gate stack integrity, then gate stack is protected, but dopant incorporation becomes ineffective and contact resistance increases
Solution Approach 1:
The patent employs extended low-temperature processing (30-120 minutes) to maintain continuous dopant activation without interruption. This continuous action at low temperature compensates for the reduced thermal energy by providing sufficient time for dopant diffusion and activation, achieving effective dopant incorporation while preserving gate stack integrity.
Solution Approach 2:
The patent changes multiple parameters simultaneously: temperature (reduced to 400-650°C), time (extended to 30-120 minutes), and atmosphere (controlled processing environment). This multi-parameter change enables effective dopant incorporation at low temperatures by compensating for reduced thermal activation through extended processing time and optimized atmospheric conditions.
3Manufacturing precision
If conventional epitaxial growth is used, then source/drain regions are formed, but growth rates are slow and processing time is extended
Solution Approach 1:
The patent replaces conventional thermal epitaxial growth with a deposition-based approach followed by in-situ crystallization. Instead of relying on slow thermal diffusion and epitaxial growth, the method uses physical vapor deposition or chemical vapor deposition to rapidly deposit amorphous semiconductor material, then activates dopants through low-temperature crystallization. This substitution dramatically increases growth rate while maintaining manufacturing precision.
Solution Approach 2:
The patent utilizes phase transition from amorphous to crystalline state during low-temperature processing. The amorphous semiconductor material is deposited rapidly, then transformed to crystalline phase through controlled heating (400-650°C) that activates dopants and forms the source/drain regions. This phase transition approach enables rapid formation with high precision, avoiding slow conventional epitaxial growth.
4Loss of time
If high temperature processing is used to form top source/drain regions, then processing time is reduced, but thermal budget increases and gate stack integrity is compromised
Solution Approach 1:
The patent changes the temperature parameter from high (above 700°C) to low (400-650°C) while extending processing time (30-120 minutes). This parameter change achieves the same dopant activation and source/drain formation without excessive thermal budget, preserving gate stack integrity. The extended time compensates for lower temperature, maintaining effectiveness while reducing thermal damage.
Solution Approach 2:
The patent performs preliminary dopant incorporation into the amorphous material before deposition, so that dopants are already in position and ready for activation. This preliminary action eliminates the need for high-temperature dopant diffusion steps, enabling low-temperature processing that reduces thermal budget while maintaining processing efficiency and gate stack integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of vertical transistors with improved contact resistance and reduced processing costs by maintaining gate stack integrity and allowing for the use of challenging dopants like gallium and antimony, while increasing the contact area and reducing thermal processing time.
Implementation Method 1
recrystallizing the doped amorphous semiconductor material with an anneal duration for substantially a millisecond duration or less to provide a doped polycrystalline source and/or drain region
Implementation Method 2
recrystallizing the doped amorphous semiconductor material with an anneal duration for substantially a millisecond duration or less
Implementation Method 3
depositing a doped amorphous semiconductor material on an upper surface of the semiconductor fin structure
Data Source
AI summary
A method of forming a semiconductor device that includes forming a vertically orientated channel in a semiconductor fin structure that is present on a supporting substrate; and depositing a doped amorphous semiconductor material on an upper surface of the semiconductor fin structure that is opposite a base surface of the semiconductor fin structure that is in contact with the supporting substrate. The method further includes recrystallizing the doped amorphous semiconductor material with an anneal duration for substantially a millisecond duration or less to provide a doped polycrystalline source and/or drain region at the upper surface of the semiconductor fin structure.