Interdigitated Vertical Transistor Stack for 3D Logic Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges in scaling transistors to single-digit nanometer nodes, leading to limitations in increasing transistor density and efficiency in two-dimensional circuits.
Innovation Solution
The development of a semiconductor device with vertically stacked transistors, where pairs of transistors are stacked over a substrate, enabling a three-dimensional circuit architecture with inter-level contacts that bypass certain gate structures to facilitate efficient electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional circuit scaling is continued, then transistor density increases, but manufacturing precision and device performance deteriorate at single-digit nanometer nodes
Solution Approach 1:
The patent transitions from two-dimensional planar transistor arrangements to three-dimensional vertically stacked transistor structures. Multiple transistor pairs are stacked along the vertical axis, with gate structures extending in multiple directions (first gate structure extending to first side, second gate structure extending to second side). This dimensional change allows continued transistor density improvement without the same scaling limitations that plague 2D architectures at single-digit nanometer nodes.
2Quantity of substance
If three-dimensional transistor stacking is implemented, then transistor density increases, but device complexity increases
Solution Approach 1:
The complex 3D transistor structure is segmented into repeating modular units. Each transistor pair consists of channel structures surrounded by gate structures in a standardized configuration. This segmentation into identical or similar repeating units simplifies the overall design and manufacturing process despite the three-dimensional arrangement, as each module can be fabricated using the same processes and then stacked.
Solution Approach 2:
The patent implements nested gate structures where first gate structures and second gate structures are positioned at different vertical levels and extend to different sides of the vertical stack. The gate structures are arranged concentrically around channel structures, with outer gate structures encompassing inner gate structures. This nesting allows efficient use of vertical space while maintaining organized, manageable structural relationships.
3Reliability
If vertically stacked transistor pairs are created, then electrical connectivity is improved, but manufacturing processes become more complex
Solution Approach 1:
The patent employs preliminary patterning and alignment processes to establish the vertical stack configuration before final transistor formation. Gate structures are positioned and aligned in advance, with first gate structures extending to first sides and second gate structures extending to second sides, creating a pre-established framework that guides subsequent manufacturing steps. This preliminary structuring simplifies later fabrication processes despite the three-dimensional complexity.
Data Source
AI summary
A semiconductor device includes a first pair of transistors over a substrate. The first pair of transistors includes a first transistor having a first gate structure over the substrate and a second transistor having a second gate structure stacked over the first transistor. A second pair of transistors is stacked over the first pair of transistors, resulting in a vertical stack perpendicular to a working surface of the substrate. The second pair of transistors includes a third transistor having a third gate structure stacked over the second transistor and a fourth transistor having a fourth gate structure stacked over the third transistor. The third gate structure extends from a central region of the vertical stack to a first side of the vertical stack. The second gate structure and the fourth gate structure extend from the central region to a second side of the vertical stack opposite the first side.