Vertical Transistor Stack Layout for Higher Density Interconnects
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Solution Overview
Problem
The challenge of increasing transistor density in integrated circuits while maintaining performance and efficiency in a limited space is not adequately addressed by existing semiconductor devices.
Innovation Solution
A semiconductor device with a multi-stack structure comprising lower and upper transistors connected via connecting layers, and source/drain structures connected through intermediate layers, allowing for improved electrical connectivity and space utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistors are arranged in a multi-stack structure to increase density, then transistor density is improved, but device complexity increases
Solution Approach 1:
The patent transitions from planar transistor arrangement to a three-dimensional multi-stack structure, stacking transistors vertically in multiple layers (first stack and second stack) to increase transistor density without proportionally increasing the footprint area. This dimensional change allows more transistors to be packed into the same space while managing complexity through systematic layering.
Solution Approach 2:
The device is divided into distinct functional segments: first transistors in a first stack, second transistors in a second stack, first source/drain structures, and second source/drain structures. Each segment is independently formed and connected through defined pathways, allowing modular assembly and simplified manufacturing of the overall complex structure.
2Reliability
If source/drain structures are connected via multiple connecting layers in a multi-stack configuration, then electrical connectivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
Connecting layers are introduced as intermediary structures between different transistor stacks and source/drain structures. These intermediate conductive pathways facilitate electrical connections across the multi-stack architecture, enabling reliable signal and power transmission between layers while providing a standardized interface that manages precision requirements.
Solution Approach 2:
The connecting layers are formed in advance during the manufacturing process, establishing predetermined conductive pathways before final transistor operations. This preliminary formation of connection structures ensures that electrical connectivity is pre-established and reduces the need for high-precision adjustments during subsequent manufacturing steps.
Data Source
AI summary
A semiconductor device includes a substrate, a transistor stack on the substrate, a first source/drain structure on a first side of the transistor stack, and a second source/drain structure on a second side of the transistor stack, where the transistor stack includes a lower transistor on the substrate, the lower transistor including a lower channel layer and a lower gate structure surrounding the lower channel layer, an upper transistor on the lower transistor, the upper transistor including an upper channel layer and an upper gate structure surrounding the upper channel layer, and a first connecting layer between the lower gate structure and the upper gate structure, and the first source/drain structure and the second source/drain structure are connected via the first connecting layer.