Vertical Multi-Transistor Stacks for Higher-Density FET Layouts
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Solution Overview
Problem
Conventional transistor-based devices using traditional layout techniques suffer from low density design applications, leading to inefficiencies and limitations in fabrication processes, making it difficult to implement various layout configurations effectively.
Innovation Solution
The development of multi-transistor stack architectures using hybrid device stacking techniques for complementary Field-Effect Transistor (FET) technologies, where multiple device stacks are fabricated together in a single monolithic semiconductor die, employing nano-sheets or Fin-FET structures with common-gate and split-gate architectures for various stack configurations such as N-over-N, P-over-P, N-over-P, and P-over-N configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional layout techniques are used for transistor-based devices, then fabrication processes are simpler, but device density is low
Solution Approach 1:
The patent transitions from planar 2D layout to vertical 3D stacking architecture, arranging multiple transistor layers (first layer, second layer, third layer) stacked vertically. This dimensional change enables significantly higher device density within the same footprint area while maintaining fabrication feasibility through systematic layer-by-layer construction processes
2Adaptability or versatility
If multiple device stacks are fabricated in a single monolithic semiconductor die, then integration capabilities are enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the semiconductor device into multiple discrete transistor layers (first layer, second layer, third layer) that can be fabricated and positioned independently. Each layer contains specific transistor configurations (e.g., NFETs in first layer, PFETs in second layer) that are segmented and stacked systematically, enabling high integration while managing precision requirements through modular construction
Solution Approach 2:
The patent implements a nested vertical structure where transistor layers are stacked one within another in a monolithic semiconductor die. The first layer is positioned at a first level, the second layer at a second level, and the third layer at a third level, creating a nested configuration that maximizes integration density while maintaining structural coherence through shared source/drain regions across layers
Data Source
AI summary
Various implementations described herein relate to a method for manufacturing, or causing to be manufactured, multiple devices packaged within a single semiconductor die. The multiple devices may have first devices that are arranged in a first multi-transistor stack with a first P-N configuration. The multiple devices may have second devices that are arranged in a second multi-transistor stack with a second P-N configuration that is different than the first P-N configuration.