Vertical Transistor Symmetrical Junction Layout for Lower Resistance
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Solution Overview
Problem
Conventional methods for forming vertical transport field effect transistors (VTFETs) face challenges in achieving symmetrical source/drain extension junctions due to geometrical constraints, leading to variations in gate length, spacer thickness, and doping profiles, which result in increased resistance and misalignments.
Innovation Solution
The method involves forming self-aligned top and bottom spacers to facilitate simultaneous formation of symmetrical source/drain extensions in VTFETs, allowing for controlled channel length and avoiding underlapped extension regions that contribute to increased resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional methods are used to form source/drain extension junctions in VTFETs, then the fabrication process can be completed, but asymmetrical junctions result in variations of gate length, spacer thickness, and doping profiles leading to increased resistance
Solution Approach 1:
The patent applies asymmetry in reverse - it uses symmetrical spacer structures (first and second spacers with matched thicknesses) to achieve symmetrical source/drain extension junctions. This symmetry ensures uniform gate length, consistent spacer thickness, and matched doping profiles, thereby reducing resistance variation and improving device reliability
Solution Approach 2:
The patent forms spacers and performs doping operations before final gate formation. By preliminarily establishing the spacer structures and performing source/drain extension doping in advance, the method ensures that subsequent gate formation does not disrupt the symmetry, thereby maintaining consistent gate length and reducing resistance variation
2Ease of manufacture
If conventional fabrication processes are used, then device formation can proceed, but geometrical constraints lead to underlapped extension regions that increase resistance
Solution Approach 1:
The patent performs source/drain extension doping before gate formation, allowing the doping process to extend fully into the channel region without being blocked by the gate structure. This preliminary doping action eliminates underlapped extension regions and reduces resistance while maintaining ease of manufacture
Solution Approach 2:
The patent transitions from planar doping to vertical doping by forming spacers that extend in the vertical dimension. This dimensional change allows doping material to access and dope the channel region from the sides, eliminating underlapped regions and reducing resistance
3Productivity
If conventional doping processes are used, then source/drain regions can be formed, but variations in doping profiles occur due to geometrical constraints
Solution Approach 1:
The patent introduces spacers as intermediary structures that mediate the doping process. These spacers provide a controlled pathway for dopant diffusion, ensuring consistent doping profiles by preventing direct contact between dopant source and channel region, thereby improving both doping efficiency and profile consistency
Solution Approach 2:
The patent changes the physical state and concentration parameters of dopants by controlling their diffusion through spacer structures. By adjusting dopant concentration, diffusion temperature, and time, the method achieves consistent doping profiles while maintaining high doping efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of symmetrical source/drain extension junctions, reducing resistance and improving the performance of VTFETs by ensuring matching thicknesses of source/drain extension regions, thus enhancing device efficiency.
Implementation Method 1
applying a single doping process that dopes the first channel portion and the second channel portion
Data Source
AI summary
A semiconductor device includes a first source/drain region on an upper surface of a semiconductor substrate that extends along a first direction to define a length and a second direction opposite the first direction to define a width. A channel region extends vertically in a direction perpendicular to the first and second directions from a first end contacting the first source/drain region to an opposing second end contacting a second source/drain region. A gate surrounds a channel portion of the channel region, and a first doped source/drain extension region is located between the first source/drain region and the channel portion. The first doped source/drain extension region has a thickness extending along the vertical direction. A second doped source/drain extension region is located between the second source/drain region and the channel portion. The second doped source/drain extension region has a thickness extending along the vertical direction that matches the first thickness.