Vertical Transistor Top Junction Control via Spacer Doping
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Solution Overview
Problem
In the fabrication of vertical field effect transistors (VFETs), the formation of top source/drain (S/D) junctions is challenging due to the need for fin recessing, which can lead to gate dielectric thinning and contamination, resulting in increased external resistance and degraded transistor performance if not done correctly.
Innovation Solution
The method involves forming a doped top spacer region around the channel fin, followed by a dopant drive-in process to create a doped top portion that forms a top junction with the main body of the channel fin, allowing for precise control over the location of the top S/D junction without recessing the fin, thus ensuring lateral overlap with the gate and preventing gate dielectric exposure to etchants.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If fin recessing is performed to form top source/drain junctions, then the top S/D junction location can be controlled, but gate dielectric thinning and contamination occur, resulting in increased external resistance and degraded transistor performance
Solution Approach 1:
The method performs preliminary doping of the spacer region before fin recessing. The spacer is doped with source/drain dopants at a concentration higher than the channel region, so that when the fin is recessed, the dopants can diffuse into the fin to form the top source/drain junctions. This preliminary doping action enables precise control of junction location while avoiding direct exposure of the gate dielectric to harsh doping conditions.
Solution Approach 2:
The spacer acts as an intermediary element that mediates the doping process. By doping the spacer first and then allowing dopant diffusion into the fin during or after recessing, the spacer serves as a protected intermediate structure that enables junction formation without requiring direct access to the fin top surface, thereby protecting the gate dielectric.
2Manufacturing precision
If fin recessing is performed to form top source/drain junctions, then the top S/D junction location can be controlled, but external resistance increases due to gate dielectric exposure
Solution Approach 1:
The method performs preliminary doping of the spacer region before fin recessing. The spacer is doped with source/drain dopants at a concentration higher than the channel region, so that when the fin is recessed, the dopants can diffuse into the fin to form the top source/drain junctions. This preliminary doping action enables precise control of junction location while avoiding direct exposure of the gate dielectric to harsh doping conditions.
Solution Approach 2:
The spacer acts as an intermediary element that mediates the doping process. By doping the spacer first and then allowing dopant diffusion into the fin during or after recessing, the spacer serves as a protected intermediate structure that enables junction formation without requiring direct access to the fin top surface, thereby protecting the gate dielectric.
3Ease of manufacture
If conventional doping methods are used to form top source/drain junctions, then the process is simple, but control over junction location and depth is poor
Solution Approach 1:
The doping process is segmented into distinct stages: first doping the spacer region separately, then allowing controlled diffusion into the fin. This segmentation allows independent optimization of dopant concentration and distribution in different regions, achieving precise control over junction location and depth while maintaining a relatively simple overall process flow.
Solution Approach 2:
The method applies different dopant concentrations to different regions: the spacer is doped at a higher concentration than the channel region. This local quality differentiation enables precise control of the doping profile, with the highly doped spacer serving as a dopant reservoir that diffuses controlled amounts of dopant into the fin to create the desired junction characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves control over the top S/D junction location, enhances transistor performance by maintaining gate dielectric integrity, and reduces external resistance by ensuring the junction extends deep enough to overlap the gate, thereby improving overall device performance.
Implementation Method 1
A dopant drive-in process is applied, wherein the dopant drive-in process is configured to drive the dopant from the top spacer region into the top portion of the channel fin
Data Source
AI summary
Embodiments of the invention are directed to a method of forming a semiconductor device. A non-limiting example of the method includes forming a channel fin over a substrate and forming a top spacer region around a top portion of the channel fin, wherein the top spacer region includes a dopant. A dopant drive-in process is applied, wherein the dopant drive-in process is configured to drive the dopant from the top spacer region into the top portion of the channel fin to create a doped top portion of the channel fin and a top junction between the doped top portion of the channel fin and a main body portion of the channel fin.