Vertical Power Transistor Trenches With Controllable Depth Difference
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Solution Overview
Problem
The production of vertical power transistors with varying trench depths is challenging due to process fluctuations and difficulty in controlling and reproducing trench depth differences, requiring multiple lithography and etching steps, making it time-consuming and costly.
Innovation Solution
A method involving the application of a dielectric layer and multiple photoresist layers with different widths, followed by photolithography and plasma etching, allows for the creation of trenches with a depth difference of at least 30% by decoupling trench width and depth, enabling controllable and cost-effective production.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple lithography and etching steps are used to produce trenches of different trench depths, then trench depth control is improved, but production time and cost increase
Solution Approach 1:
The patent segments the trench formation process into two distinct stages: first forming shallow trenches to a controlled depth in the dielectric layer, then forming deep trenches through the dielectric layer to the semiconductor substrate. This segmentation allows each etching step to be optimized independently, achieving precise depth control without requiring multiple iterative lithography cycles.
Solution Approach 2:
The patent introduces a vertical dimension to the process by creating trenches of different depths within the same dielectric layer structure. By utilizing the depth dimension selectively (some trenches stopping at dielectric interface, others continuing to substrate), the method achieves varied trench depths without requiring multiple lateral lithography steps.
2Manufacturing precision
If multiple lithography and etching steps are used to produce trenches of different trench depths, then trench depth control is improved, but production cost increases
Solution Approach 1:
The patent merges the formation of shallow and deep trenches into a single integrated process flow using one lithography step. By patternning both shallow and deep trench regions simultaneously and then performing sequential etching, the method eliminates the need for separate lithography and etching cycles for each trench type, thereby reducing production cost.
Solution Approach 2:
The patent performs preliminary action by forming the complete trench pattern in the dielectric layer during the first etching step, creating both shallow and deep trench regions in advance. This preliminary structuring allows the second etching step to simply complete the deep trenches without requiring additional lithography preparation, reducing overall process cost.
3Speed
If trench width is varied to control etching rate, then etching rate is improved, but trench depth uniformity deteriorates
Solution Approach 1:
The patent applies local quality by maintaining uniform trench width across all trench regions while allowing different trench depths. The single lithography step patterns all trenches with identical width, ensuring uniform etching rate, while the selective etching process creates different final depths based on local requirements (shallow vs. deep trench regions).
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the production of vertical power transistors with controllable, large trench depths, reducing production time and costs while maintaining high breakdown field strength and small cell size.
Implementation Method 1
creating first openings having a first width in the first photoresist layer with the aid of first photolithography
Implementation Method 2
etching the first regions of the dielectric layer to at least a specified depth of the dielectric layer
Data Source
AI summary
A method for producing vertical power transistors. The method includes: applying a dielectric layer to a semiconductor material; applying a first photoresist layer to the dielectric layer; creating first openings having a first width in the first photoresist layer exposing first regions of the dielectric layer; etching the first regions of the dielectric layer to at least a specified depth of the dielectric layer such that a first structured dielectric layer is created; removing the first photoresist layer; applying a second photoresist layer to the first structured dielectric layer; creating second openings having a second width in the second photoresist layer exposing second regions of the dielectric layer; etching the second regions of the dielectric layer up to a surface of the semiconductor material such that a second structured dielectric layer is created; removing the second photoresist layer; and creating the first trenches and the second trenches.