Vertical Transistor Fabrication via Trench Isolation
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Solution Overview
Problem
The challenge in semiconductor device manufacturing lies in reducing the number of processes required to form vertical transistors in both the cell and peripheral circuit regions, while maintaining the performance characteristics of planar transistors, which is currently hindered by the increased complexity and cost associated with forming vertical transistors in both regions simultaneously.
Innovation Solution
A semiconductor device and method that involves forming island-shaped vertical gate structures on a semiconductor substrate with a cell region and a peripheral circuit region, using polysilicon and metal silicide layers for contact pads and gate electrodes, and employing buried contact plugs and isolation layers to electrically connect the transistors, thereby reducing the number of processing steps and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertical transistors are formed in both cell region and peripheral circuit region, then integration density is increased and manufacturing processes are shortened, but device characteristics of peripheral circuit transistors are degraded
Solution Approach 1:
The patent applies different transistor structures to different regions: vertical transistors are formed in the cell region where high integration density is critical, while planar transistors are formed in the peripheral circuit region where device characteristics are paramount. This regional differentiation allows each region to optimize for its specific functional requirements without compromising the other.
Solution Approach 2:
The semiconductor device is segmented into distinct functional regions (cell region and peripheral circuit region) with different transistor architectures. The cell region uses vertical transistors for high density, while the peripheral circuit region uses planar transistors for high performance, creating a heterogeneous device structure that balances both density and performance requirements.
2Device complexity
If vertical transistors are formed in both cell region and peripheral circuit region, then the number of manufacturing processes is reduced, but manufacturing cost increases due to process complexity
Solution Approach 1:
The patent merges the formation processes of cell transistors and peripheral circuit transistors into a unified manufacturing sequence. By forming vertical transistors in the cell region and planar transistors in the peripheral circuit region through integrated process steps, the method reduces the total number of separate manufacturing processes compared to forming them independently.
Solution Approach 2:
The patent performs preliminary actions by forming the vertical transistor structures in the cell region first, establishing a foundation that enables subsequent formation of planar transistors in the peripheral circuit region. This sequencing allows process integration while maintaining the distinct structural requirements of each transistor type.
Data Source
AI summary
There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures. A bit line separation insulating layer and a peripheral circuit isolation layer are formed inside the bit line separation trench and the peripheral circuit trench, respectively.