Vertical Transistor via Wafer-Level Bonding
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Solution Overview
Problem
Current semiconductor fabrication methods face challenges in increasing the density of integration for field-effect transistors (FETs) suitable for highly-integrated architectures, particularly in forming efficient and compact transistor structures for applications like DRAM and SRAM.
Innovation Solution
The method involves wafer level bonding technologies, where a first assembly with a buried contact is bonded to a second assembly to form a hybrid structure, with a semiconductor pillar surrounded by an insulative wall, and subsequent formation of a vertical transistor with a gate dielectric and conductive gate material, enabling simplified contact formation to the bottom source/drain region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional FET fabrication methods are used, then manufacturing processes are well-established, but density of integration cannot be increased sufficiently for highly-integrated architectures
Solution Approach 1:
The fabrication process is divided into separate assemblies that are formed independently and then bonded together. The first assembly includes the semiconductor substrate with source/drain regions and buried contact, while the second assembly includes the gate structure. This segmentation allows each assembly to be optimized separately and enables higher integration density through wafer-level bonding.
Solution Approach 2:
The invention transitions from planar FET structures to vertically-integrated 3D architectures by stacking multiple assemblies in the vertical dimension. The wafer-level bonding approach enables stacking of multiple FET layers, achieving higher integration density by utilizing the third dimension rather than expanding only in the planar direction.
2Productivity
If wafer level bonding is used to form hybrid structures, then density of integration increases, but manufacturing process complexity increases
Solution Approach 1:
Multiple assemblies are prepared in advance with pre-formed structures including source/drain regions, buried contacts, and gate dielectrics before bonding. The first assembly is prepared with semiconductor material and doped regions, and the second assembly is prepared with gate structures, allowing parallel processing and reducing overall manufacturing complexity despite the multi-step bonding process.
Solution Approach 2:
A bonding interface is introduced as an intermediary between the first and second assemblies. This bonding interface includes bonding pads and connection structures that facilitate the wafer-level bonding process, enabling the joining of complex assemblies while maintaining manufacturing feasibility through standardized bonding procedures.
3Ease of manufacture
If vertical transistor structures are formed with buried contacts, then contact formation to bottom source/drain is simplified, but device structure complexity increases
Solution Approach 1:
The conventional approach of forming contacts to bottom source/drain regions from above is inverted by creating buried contacts within the first assembly before bonding to the second assembly. This inversion allows direct access to the bottom source/drain regions through the bonding interface, simplifying contact formation despite the increased vertical structure complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of densely integrated FETs with improved transistor architecture, enhancing the density of integration and simplifying the formation of contacts, which is beneficial for advanced memory and logic applications.
Implementation Method 1
The treatment utilized to induce the covalent bonding may be a thermal treatment. In some aspects, such thermal treatment may utilize a temperature in excess of 800° C.
Implementation Method 2
one or both of the silicon dioxide surfaces may be subjected to a plasma treatment prior to the thermal treatment, and in such aspects the temperature of the thermal treatment may be reduced to a temperature within a range of from about 150° C. to about 200° C.
Data Source
AI summary
Some embodiments include methods in which a structure has a first semiconductor material over a dielectric region, a second semiconductor material under the dielectric region, an insulative wall laterally surrounding a volume of the first semiconductor material, and a first doped region along a lower surface of the first semiconductor material. The first semiconductor material is patterned to form a pillar within a tub. The pillar has top and bottom portions. An upper doped region is formed within the pillar top portion. A dielectric liner is formed to extend along the pillar, and to extend along the bottom of the tub. Conductive gate material is formed within the tub and over the dielectric liner. The lower and upper doped regions within the pillar are first and second source/drain regions, respectively, and the conductive gate material includes a transistor gate which gatedly couples the first and second source/drain regions.