Vertical Transistor Contact Resistance Reduction via Wrap-Around Metal
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Solution Overview
Problem
In semiconductor device fabrication, closely packed vertical transistors face challenges in reducing contact resistance while preventing electrical shorts between the source/drain epitaxy and the metal gate, particularly as feature sizes decrease and aspect ratios increase.
Innovation Solution
A method involving the formation of a wrap-around contact metal on all sides of the top source/drain epitaxy and a dual-purpose nitride liner to confine the epitaxy in a trench, preventing electrical shorts and reducing contact resistance by increasing the epitaxy contact area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If closely packed vertical transistors are fabricated with increased device density, then device footprint is reduced, but contact resistance increases and electrical shorts occur between source/drain epitaxy and metal gate
Solution Approach 1:
The patent transitions from planar contact geometry to three-dimensional wrap-around contact geometry. The contact metal extends around the sidewalls of the semiconductor fin structure, utilizing the vertical dimension to increase contact area without expanding the horizontal footprint. This dimensional transition allows closely packed transistors to maintain low contact resistance while achieving high device density.
Solution Approach 2:
The contact metal is nested around the semiconductor fin structure, with the contact material conformally coating the sidewalls and wrapping around the fin. This nested configuration allows the contact to surround the active region from multiple directions, maximizing electrical contact area while maintaining compact transistor spacing and preventing electrical shorts to the gate.
2Productivity
If feature sizes are decreased to increase device density, then device footprint is reduced, but electrical shorts between source/drain contact and metal gate occur
Solution Approach 1:
The patent applies different material properties to different regions of the transistor structure. The contact metal is selectively positioned and shaped to provide optimal electrical contact in the source/drain regions while being prevented from contacting the gate. The wrap-around configuration creates localized high-quality electrical contact where needed while maintaining isolation where required, preventing electrical shorts even as feature sizes decrease.
Solution Approach 2:
The conformal dielectric layer acts as an intermediary barrier between the contact metal and the semiconductor fin structure. This dielectric layer is selectively removed only in the contact regions, allowing the contact metal to reach the source/drain epitaxy while the remaining dielectric prevents electrical shorts to the gate. This intermediary approach enables precise control of electrical connectivity in closely packed vertical transistors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces contact resistance and prevents electrical shorts between the source/drain contact and the metal gate, enhancing the performance of closely packed vertical transistors.
Implementation Method 1
A top epitaxy region is formed on the exposed top surface and sidewalls of the semiconductor fin and the exposed sidewall of the dielectric layer, an extension of the top epitaxy region filling the recessed opening
Data Source
AI summary
A method of forming a semiconductor device and resulting structures having closely packed vertical transistors with reduced contact resistance by forming a semiconductor structure on a doped region of a substrate, the semiconductor structure including a gate formed over a channel region of a semiconductor fin. A liner is formed on the gate and the semiconductor fin, and a dielectric layer is formed on the liner. Portions of the liner are removed to expose a top surface and sidewalls of the semiconductor fin and a sidewall of the dielectric layer. A recessed opening is formed by recessing portions of the liner from the exposed sidewall of the dielectric layer. A top epitaxy region is formed on the exposed portions of the semiconductor fin and dielectric layer such that an extension of the top epitaxy region fills the recessed opening. The top epitaxy region is confined between portions of the liner.