Vertical Logic Transistors With Backside S/D for Higher Density
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Solution Overview
Problem
The challenge in the semiconductor industry is to optimize the performance and density of transistors on integrated circuits while minimizing short-channel effects and thermal limitations, particularly by exploring alternative architectures such as vertical transistors with backside source or drain regions.
Innovation Solution
The implementation of vertical transistors with backside source or drain regions, where the source and drain regions are positioned on opposite surfaces of the substrate, allowing for increased transistor density and reduced short-channel effects, and operating these transistors at low temperatures to further optimize performance by reducing gate length and thermal energy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional planar transistors are used, then manufacturing is simpler, but transistor density and performance are limited
Solution Approach 1:
The patent transitions from traditional planar (2D) transistor architecture to a vertical (3D) transistor structure where the channel extends through the thickness of the semiconductor layer. This dimensional change allows multiple transistors to be stacked vertically, dramatically increasing transistor density without proportionally increasing the chip area, thus resolving the contradiction between density and complexity.
Solution Approach 2:
The vertical transistor structure nests multiple functional layers within a compact footprint: the channel region is surrounded by gate electrodes on multiple sides, and source/drain regions are positioned at opposite surfaces. This nested arrangement maximizes the use of available space, enabling high density while maintaining manageable structural complexity.
2Productivity
If transistor size is reduced to increase density, then capacity increases, but short-channel effects worsen
Solution Approach 1:
By extending the channel in the vertical dimension rather than shrinking it laterally, the patent achieves density improvement without reducing the effective channel length in the current-carrying direction. The vertical channel structure provides better electrostatic control over the charge carrier flow, suppressing short-channel effects while maintaining high density.
Solution Approach 2:
The vertical transistor employs an asymmetric structure where the channel depth and gate wrap-around geometry provide enhanced control. The gate electrodes surround the channel from multiple directions, creating an asymmetric field distribution that improves electrostatic control and reduces short-channel effects compared to symmetric planar structures.
3Speed
If gate length is reduced to improve performance, then speed increases, but thermal energy and short-channel effects increase
Solution Approach 1:
The vertical channel structure allows the effective channel length to be controlled independently of the lateral footprint. By optimizing the vertical channel depth rather than shrinking lateral dimensions, the patent achieves fast switching speeds while maintaining better thermal management and reduced short-channel effects, as the heat dissipation path is extended in the vertical direction.
Data Source
AI summary
IC devices with logic circuits using vertical transistors with backside source or drain (S/D) regions, and related assemblies and methods, are disclosed herein. An example vertical transistor includes an elongated structure (e.g., a nanoribbon) of one or more semiconductor materials extending between a first side (e.g., a back side) and an opposing second side (e.g., a front side) of a substrate. The first S/D region of the transistor may be provided at the first side of the substrate, while the second S/D region of the transistor may be provided at the second side, with the channel region of the transistor being the portion of the elongated structure between the first and second S/D regions. Implementing various logic circuits using vertical transistors with backside S/D regions may provide a promising way to increasing densities of transistors on the limited real estate of semiconductor chips and/or decreasing short-channel effects associated with continuous scaling of IC components.