Vertical Access Transistors With Gate-All-Around Channel Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional planar thin film transistors face limitations in scaling due to material properties and process control, and vertical devices suffer from insufficient source/drain-to-gate overlap, which degrades device performance.
Innovation Solution
The development of vertical field effect transistors with a self-aligned cylindrical vertical channel and a gate-all-around configuration, featuring a shared gate electrode among a row of transistors, to enhance channel control and increase channel width per device area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional planar thin film transistors are used, then manufacturing simplicity is maintained, but device performance and scalability are limited
Solution Approach 1:
The patent transitions from conventional planar (2D) transistor structures to vertical (3D) transistor structures by stacking multiple layers including semiconductor layers, dielectric layers, and metal layers vertically. This dimensional change increases the effective channel width per device area and improves source/drain-to-gate overlap, thereby enhancing device performance and on-current while maintaining manufacturing feasibility through adapted fabrication processes
2Reliability
If vertical transistor structures are adopted, then channel control and on-current are improved, but source/drain-to-gate overlap remains insufficient
Solution Approach 1:
The patent implements a gate-all-around configuration where the gate electrode is positioned to surround the channel region vertically and laterally. The gate electrode is formed between the source and drain electrodes in the vertical stack, creating nested positioning where the gate is enclosed within the structure defined by source and drain regions. This nesting geometry maximizes the overlap between source/drain regions and the gate, improving electrostatic control and on-current while maintaining manufacturability
Data Source
AI summary
A plurality of vertical stacks may be formed over a substrate. Each of the vertical stacks includes, from bottom to top, a bottom electrode, a dielectric pillar, and a top electrode. A continuous active layer may be formed over the plurality of vertical stacks. A gate dielectric layer may be formed over the continuous active layer. The continuous active layer and the gate dielectric layer may be patterned into a plurality of active layers and a plurality of gate dielectrics. Each of the plurality of active layers laterally surrounds a respective one of the vertical stacks that are arranged along a first horizontal direction, and each of the plurality of gate dielectrics laterally surrounds a respective one of the active layers. Gate electrodes may be formed over the plurality of gate dielectrics.