Vertical Transistors With Multiple Gate Thicknesses

Solution Overview

Problem

Existing semiconductor fabrication methods face challenges in optimizing gate resistance and device density for vertical field effect transistors (VFETs), as thicker gates improve performance but limit minimum transistor pitch, while thinner gates enhance density but compromise performance.

Innovation Solution

The method involves forming VFETs with multiple gate thicknesses, where thicker gates are used in performance regions for improved performance and thinner gates in density regions to maximize pitch and density, respectively, without reducing fin thickness or gate dielectric thickness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If thicker gates are used in VFETs, then performance is improved, but minimum transistor pitch increases

Engineering Contradiction:

ImproveperformanceVSAvoidtransistor pitch

Core Design Contradiction:

ReliabilityVSLength of moving object

Solution Approach 1:

The patent applies local quality by implementing different gate thicknesses in different regions of the semiconductor device. Specifically, first gate structures with a first thickness are formed in performance regions, while second gate structures with a second thickness are formed in density regions. This allows each region to have optimized characteristics for its specific function.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent segments the semiconductor device into distinct performance regions and density regions, each with independently optimized gate structures. The performance regions contain gate structures with thicker gates for improved performance, while density regions contain gate structures with thinner gates for reduced pitch, allowing the overall device to achieve both high performance and high density.

Inventive Principle:

Principle #1Segmentation

2Quantity of substance

If thinner gates are used in VFETs, then device density is improved, but performance deteriorates

Engineering Contradiction:

Improvedevice densityVSAvoidperformance

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent applies local quality by implementing different gate thicknesses in different regions of the semiconductor device. Specifically, first gate structures with a first thickness are formed in performance regions, while second gate structures with a second thickness are formed in density regions. This allows each region to have optimized characteristics for its specific function.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent segments the semiconductor device into distinct performance regions and density regions, each with independently optimized gate structures. The performance regions contain gate structures with thicker gates for improved performance, while density regions contain gate structures with thinner gates for reduced pitch, allowing the overall device to achieve both high performance and high density.

Inventive Principle:

Principle #1Segmentation

3Reliability

If gate thickness is increased, then gate resistance is reduced, but transistor pitch must increase

Engineering Contradiction:

Improvegate resistanceVSAvoidtransistor pitch

Core Design Contradiction:

ReliabilityVSLength of moving object

Solution Approach 1:

The patent applies local quality by implementing different gate thicknesses in different regions of the semiconductor device. Specifically, first gate structures with a first thickness are formed in performance regions, while second gate structures with a second thickness are formed in density regions. This allows each region to have optimized characteristics for its specific function.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent segments the semiconductor device into distinct performance regions and density regions, each with independently optimized gate structures. The performance regions contain gate structures with thicker gates for improved performance, while density regions contain gate structures with thinner gates for reduced pitch, allowing the overall device to achieve both high performance and high density.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS10811508B2Vertical transistors having multiple gate thicknesses for optimizing performance and device density

Publication Date: 2020.10.20 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

Embodiments of the invention are directed to methods of forming a configuration of semiconductor devices. A non-limiting example method includes forming a first channel fin structure over a performance region of a major surface of a substrate. A first gate structure is formed along at least a portion of a sidewall surface of the first channel fin structure, where the first gate structure includes a first gate thickness dimension. A second channel fin structure is formed over a density region of the major surface of the substrate. A second gate structure is formed along at least a portion of a sidewall surface of the second channel fin structure, where the second gate structure includes a second gate thickness dimension that is less than the first gate thickness dimension.