Vertical Transmon Qubit with 3D Capacitor
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Solution Overview
Problem
Existing transmon qubits occupy a large amount of space due to the size of planar capacitors and are subject to low-temperature and process constraints in manufacturing, particularly with Josephson junctions made from shadow evaporated aluminum and aluminum oxide.
Innovation Solution
The fabrication of a vertical transmon qubit device with a vertical Josephson junction involves removing portions of the single-crystalline silicon substrate to reduce the shunting capacitor footprint, allowing for improved scaling and integration into circuits while maintaining a low-loss environment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a planar capacitor is used in transmon qubits, then the qubit can be fabricated with conventional processes, but the capacitor occupies a large area reducing device compactness
Solution Approach 1:
The patent transitions from a planar (2D) capacitor geometry to a vertical (3D) capacitor geometry. The vertical capacitor uses stacked superconducting plates separated by a dielectric layer, utilizing the third dimension (vertical stacking) to achieve high capacitance in a small footprint. This dimensional change resolves the contradiction by maintaining ease of manufacture through standard thin-film deposition while dramatically reducing the lateral area occupied by the capacitor.
Solution Approach 2:
The vertical capacitor structure embeds multiple functional layers within a compact vertical stack. The dielectric material is nested between superconducting plates, and the entire capacitor assembly is integrated within the qubit structure. This nesting approach allows the capacitor to achieve high capacitance value while occupying minimal lateral space, resolving the area constraint.
2Reliability
If shadow evaporated aluminum and aluminum oxide are used to create Josephson junctions, then low critical current and low loss can be achieved, but low-temperature and process constraints are imposed
Solution Approach 1:
The patent modifies the fabrication parameters by using sputter deposition instead of shadow evaporation, and by controlling the oxidation process separately. This parameter change allows the Josephson junction to maintain low loss characteristics while being compatible with standard semiconductor fabrication processes that operate at higher temperatures and offer greater process flexibility. The separate oxidation step enables precise control of the tunnel barrier properties without being constrained by the limitations of shadow evaporation.
3Area of stationary object
If the transmon qubit size is reduced for better integration, then scaling is improved, but surface and dielectric loss increase
Solution Approach 1:
The vertical capacitor geometry concentrates the electric field in the vertical dimension rather than spreading it laterally. This allows the qubit to achieve the required capacitance in a compact footprint while maintaining adequate separation between field regions, thereby reducing surface and dielectric losses. The vertical stacking enables high capacitance density without increasing lateral dimensions, resolving the contradiction between size reduction and loss minimization.
Solution Approach 2:
The patent uses high-quality superconducting materials and optimized dielectric layers in critical regions where electric field concentration occurs. By locally enhancing the quality of materials at the Josephson junction and capacitor interfaces, the design maintains low loss characteristics even as the overall device size is reduced for better integration and scaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The vertical transmon qubit achieves reduced decoherence, smaller capacitor footprint, and improved frequency variability, enabling efficient scaling and integration into chip manufacturing processes.
Implementation Method 1
A Josephson junction generally manifests the Josephson effect of a supercurrent, where current can flow indefinitely across a Josephson junction without an applied voltage
Implementation Method 2
A Josephson junction can be created by weakly coupling two superconductors (a material that conducts electricity without resistance), for example, by a tunnel barrier
Data Source
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AI summary
A chip surface base device structure (300) comprises a first superconducting material (112) physically coupled to a crystalline substrate (206A, 206B), wherein the crystalline substrate is physically coupled to a second superconducting material (304B), wherein the second superconducting material is physically coupled to a second crystalline substrate (102). In one implementation, the chip surface base device structure also comprises a vertical Josephson junction located in a via of the crystalline substrate, the vertical Josephson junction comprising the first superconducting material, a tunnel barrier, and the second superconducting material. In one implementation, the chip surface base device structure also comprises a transmon qubit comprising the vertical Josephson junction and a capacitor formed between the first superconducting material and the second superconducting material.