Vertical Transport FETs with Equal Gate Stack Thicknesses
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Solution Overview
Problem
In high-k/metal gate fabrication processes for vertical transport FETs, achieving consistent gate thicknesses between device types is challenging, which affects gate variation, encapsulation, and isolation.
Innovation Solution
The use of selective etching of one gate metal relative to others in distinct gate stacks between n-type and p-type FETs, allowing for the formation of thicker gate stacks to match the thickness of other device types, with different work function metals and a thickness matching layer to ensure uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If selective etching of gate metals is performed to achieve different gate thicknesses for n-type and p-type FETs, then voltage threshold control is improved, but gate thickness uniformity deteriorates
Solution Approach 1:
The patent changes the thickness parameter of the thickness matching layer to match the gate stack thickness of the first device type. By adjusting this parameter, the overall gate stack thickness of the second device type becomes equal to that of the first device type, resolving the thickness uniformity issue while maintaining voltage threshold control through selective etching
Solution Approach 2:
The thickness matching layer acts as an intermediary element between the second-type work function layer and the gate dielectric. This intermediate layer compensates for the thickness difference created by selective etching, enabling both voltage threshold control and gate thickness uniformity
2Manufacturing precision
If thicker gate stacks are formed to match other device types, then gate thickness uniformity is improved, but device complexity increases
Solution Approach 1:
The gate stack of the second device type is segmented into distinct functional layers: second-type work function layer, thickness matching layer, and gate dielectric. This segmentation allows each layer to serve its specific purpose while maintaining overall thickness uniformity
Solution Approach 2:
The thickness matching layer is applied locally only to the second device type, providing the necessary thickness compensation without affecting the first device type. This localized approach maintains gate thickness uniformity across different device types without unnecessarily increasing complexity
Data Source
AI summary
Integrated chips include a first semiconductor device and a second semiconductor device. The first semiconductor device includes a semiconductor channel, a first-type work function layer formed from a first material on the semiconductor channel, and a second-type work function layer formed from a second material on the first-type work function later layer. The second semiconductor device includes a semiconductor channel, a second-type work function layer formed the second material on the semiconductor channel, and a thickness matching layer formed on the second-type work function layer of the second semiconductor device, the thickness matching layer having a thickness roughly equal to a thickness of the first-type work function layer.


