Vertical Transport FET Logic Circuits for High Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional lateral FET structures in logic circuits face challenges in reducing circuit footprint and achieving higher circuit density due to layout and interconnection limitations, particularly in advanced CMOS logic circuits where diffusion breaks are necessary for isolation, leading to increased circuit area and reduced density.
Innovation Solution
The use of vertical transport field effect transistors (VTFETs) in logic circuits, which allow for the design of single-CPP inverters, two-CPP NOR logic gates, and three-CPP NAND logic gates, eliminating the need for extra diffusion breaks and optimizing circuit layout to achieve higher density by utilizing vertical fin structures and distinct conductive levels for improved interconnectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional lateral FET structures are used in logic circuits, then the circuit layout is simpler to implement, but the circuit footprint is larger and circuit density is reduced due to necessary diffusion breaks for isolation
Solution Approach 1:
The patent transitions from lateral FET structures (current flow in the plane of the substrate) to vertical FET structures (current flow perpendicular to the substrate). This dimensional change allows current to flow vertically through the channel, eliminating the need for lateral diffusion breaks and enabling higher circuit density while maintaining manufacturing feasibility through adapted fabrication processes
2Reliability
If diffusion breaks are introduced for isolation in lateral FET circuits, then device isolation is achieved, but circuit area increases and density decreases
Solution Approach 1:
By moving to vertical FET architecture, the patent achieves device isolation through vertical stacking and selective doping in the vertical channel, eliminating the need for lateral diffusion breaks. This allows adjacent logic gates to be placed closer together horizontally, significantly improving circuit density while maintaining proper device isolation through the vertical structure design
3Area of stationary object
If vertical transport FETs are used to reduce circuit footprint, then circuit density is improved, but circuit and layout complexity increases
Solution Approach 1:
The patent segments the circuit into distinct vertical levels (first level with n-FETs, second level with p-FETs, third level for interconnections). This segmentation allows each level to be optimized independently while maintaining overall circuit functionality, making the complex vertical layout more manageable and potentially enabling standardized design modules that could simplify future circuit design
Data Source
AI summary
Logic circuits, or logic gates, are disclosed comprising vertical transport field effect transistors and one or more active gates, wherein the number of CPP's for the logic circuit, in isolation, is equal to the number of active gates. The components of the logic circuit can be present in at least three different vertical circuit levels, including a circuit level comprising at least one horizontal plane passing through a conductive element that provides an input voltage to the one or more gate structures and another conductive element that provides an output voltage of the logic circuit, and another circuit level that comprises a horizontal plane passing through a conductive bridge from the N output to P output of the field effect transistors. Such logic circuits can include single-gate inverters, two-gate inverters, NOR2 logic gates, and NAND3 logic gates, among other more complicated logic circuits.