Vertical Trench Capacitor Co-Integration for Compact IC Layouts
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Solution Overview
Problem
Existing integrated-circuit architectures face challenges with bulky capacitive elements and costly, complex fabrication processes that hinder the efficient co-integration of capacitive elements, memory cells, and high voltage MOS transistors.
Innovation Solution
A method involving the formation of trenches and wells in a semiconductor substrate, with insulating layers and conductive materials to create capacitors and memory cells that share fabrication steps with high voltage MOS transistors, thereby reducing complexity and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If capacitive elements are implemented using conventional planar structures, then fabrication is simpler, but capacitance per unit area is limited and component area is large
Solution Approach 1:
The patent transitions from planar (2D) capacitor structures to vertically structured (3D) capacitors with trenches extending into the substrate. This dimensional change increases the effective capacitance area without proportionally increasing the footprint area, thereby increasing capacitance per unit area while reducing overall component area
Solution Approach 2:
The vertically structured capacitor is integrated within the same substrate and process flow as memory cells and transistors. The capacitor trenches are formed alongside memory cell structures, and shared layers (insulating layers, conductive layers) are deposited concurrently, nesting multiple functions within a compact vertical architecture
2Manufacturing precision
If dedicated fabrication steps are implemented for each component type, then manufacturing precision is maintained, but process complexity and cost increase
Solution Approach 1:
The patent combines the fabrication processes for capacitors, memory cells, and transistors into a unified process flow. Shared steps include trench formation, insulating layer deposition, and conductive layer patterning. By merging these previously separate processes, the patent reduces overall process complexity and cost while maintaining manufacturing precision through consistent process parameters
Solution Approach 2:
The fabrication process is designed to be universal, accommodating multiple component types (capacitors, memory cells, transistors) using the same sequence of steps and materials. The insulating layers and conductive layers serve multiple functions simultaneously - forming capacitor structures, memory cell gates, and transistor components - thereby eliminating the need for dedicated process steps for each component type
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the integration of capacitive elements, memory cells, and high voltage MOS transistors on a common substrate with increased capacitance per unit area and reduced fabrication costs, improving the efficiency and compactness of integrated-circuit architectures.
Implementation Method 1
each of the first and second trenches includes a central conductor insulated by a first insulating layer
Implementation Method 2
a first layer of conductive material on the second insulating layer, said first layer of conductive material electrically connected to the first central conductor, wherein the first layer of conductive material and first central conductor form a second plate of the capacitor
Implementation Method 3
a semiconductor substrate; a capacitor supported by the semiconductor substrate; and a memory cell supported by the semiconductor substrate
Data Source
AI summary
First and second wells are formed in a semiconductor substrate. First and second trenches in the first second wells, respectively, each extend vertically and include a central conductor insulated by a first insulating layer. A second insulating layer is formed on a top surface of the semiconductor substrate. The second insulating layer is selectively thinned over the second trench. A polysilicon layer is deposited on the second insulating layer and then lithographically patterned to form: a first polysilicon portion over the first well that is electrically connected to the central conductor of the first trench to form a first capacitor plate, a second capacitor plate formed by the first well; and a second polysilicon portion over the second well forming a floating gate electrode of a floating gate transistor of a memory cell having an access transistor whose control gate is formed by the central conductor of the second trench.