Vertical Semiconductor Trench Layout for Compact Field Termination
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Solution Overview
Problem
Existing vertical semiconductor devices face challenges with large area occupation by field termination, increasing manufacturing costs and thermal budget due to complex processing requirements for field termination in diodes and other semiconductor devices.
Innovation Solution
Incorporating a trench in the semiconductor body that electrically isolates portions of the second semiconductor region, allowing it to fully cover the first semiconductor region, reducing the need for extensive masking and etching steps, and enabling a more efficient use of the semiconductor body area for active regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a field termination is implemented by increasing the distance between the second semiconductor region and channel stopper region, then premature lateral breakdown is prevented, but a relatively large area of the semiconductor body is occupied which does not effectively contribute to the active area
Solution Approach 1:
The second semiconductor region is divided into an inner portion and an outer portion that are electrically isolated from each other by a trench. This segmentation allows the outer portion to provide field termination functionality while the inner portion remains available as active area, thus resolving the contradiction between preventing lateral breakdown and maximizing active area.
2Manufacturing precision
If masking layer, lithography and etching steps as well as implanting and driving in ions are applied to form second semiconductor region as a diffusion in the epitaxial layer, then the second semiconductor region is properly formed, but the thermal budget, process spread, energy consumption and manufacturing costs increase
Solution Approach 1:
The second semiconductor region is formed as a structured region during the epitaxial growth process itself, rather than requiring subsequent ion implantation and drive-in steps. This preliminary formation of the doped region during growth reduces the number of high-temperature processing steps required, thereby reducing thermal budget and manufacturing costs while maintaining proper formation of the second semiconductor region.
3Reliability
If the second semiconductor region is structured into the epitaxial layer as a diffusion well, then the PN-junction is properly formed, but extensive masking and etching steps are required increasing device complexity
Solution Approach 1:
The second semiconductor region with the desired doping profile is formed directly during the epitaxial growth process by controlling dopant incorporation, eliminating the need for subsequent ion implantation, masking, and etching steps. This preliminary formation simplifies the overall device structure and reduces processing complexity while ensuring proper PN-junction formation.
Solution Approach 2:
The complex ion implantation and drive-in processing steps are extracted and removed from the manufacturing sequence. Instead, the doping is achieved in-situ during epitaxial growth, which takes out the need for separate high-temperature diffusion steps and reduces the overall number of processing operations required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the area required for field termination, lowers manufacturing costs and thermal budget, and enhances the efficiency of the semiconductor device production process while maximizing the active area.
Implementation Method 1
an epitaxial layer grown on said substrate. The epitaxial layer comprises a first semiconductor region of a first conductivity type, and a second semiconductor region of a second conductivity type
Data Source
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AI summary
Aspects of the present disclosure generally relate to a vertical semiconductor device. Aspects of the present disclosure also relate to a method for manufacturing such vertical semiconductor device. The semiconductor device comprises a semiconductor body comprising a substrate and an epitaxial layer arranged on said substrate, wherein the epitaxial layer comprises a first semiconductor region of a first conductivity type, and a second semiconductor region of a second conductivity type different from the first conductivity type, wherein the second semiconductor region is arranged opposite to the substrate with respect to the first semiconductor region, and wherein, viewed in a first direction from the epitaxial layer to the substrate, the first semiconductor region and the second semiconductor region each extend across an entire area of the semiconductor body. The semiconductor device further comprises a trench arranged in the semiconductor body, wherein said trench extends through the second semiconductor region and at least partially into the first semiconductor region, thereby dividing the second semiconductor region into an inner portion and an outer portion that are mutually electrically isolated, and a first conductive contact arranged on the second semiconductor region and being configured to enable electrically accessing the inner portion.