Vertical Trench-Gate Transistor Doping Profile for Shield Resistance
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Solution Overview
Problem
Existing shielded trench-gate transistors face challenges in achieving low shield and gate resistance while maintaining high breakdown voltage, as increased shield resistance due to shrinking semiconductor dimensions adversely affects device performance, and adding additional shield contacts complicates packaging and increases die size.
Innovation Solution
The implementation of a vertical transistor design with perpendicularly intersecting trenches, where the end portions of semiconductor mesas have a higher doping concentration than the central portions, reducing three-sided depletion and enhancing breakdown voltage without adding additional gate runners.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional shield contacts are added to reduce shield resistance, then shield resistance decreases, but device complexity increases and die size increases
Solution Approach 1:
The patent applies local quality by creating a non-uniform doping profile within the semiconductor mesa, where the first and second portions have a first doping concentration and the third portion has a second doping concentration. This localized variation in electrical properties reduces shield resistance in specific regions without requiring additional shield contacts, thereby maintaining low shield resistance while avoiding increased device complexity.
2Reliability
If additional shield contacts are added to reduce shield resistance, then shield resistance decreases, but die size increases
Solution Approach 1:
The patent uses local quality by implementing a non-uniform doping profile where specific portions of the semiconductor mesa have different doping concentrations. This approach reduces shield resistance through localized electrical property modification rather than adding more contacts, thereby achieving low shield resistance without increasing die size.
3Reliability
If intersecting trenches are used to place multiple shield contacts, then shield resistance decreases, but breakdown voltage decreases
Solution Approach 1:
The patent applies local quality by creating a non-uniform doping profile in the semiconductor mesa with different doping concentrations in different portions. This localized modification reduces shield resistance through improved electrical coupling without requiring intersecting trenches, thereby maintaining both low shield resistance and high breakdown voltage capability.
Solution Approach 2:
The patent changes the doping concentration parameter within the semiconductor mesa, creating regions with different doping levels. This parameter variation optimizes the electrical properties to reduce shield resistance while preserving the breakdown voltage characteristics, avoiding the need for intersecting trench structures.
4Length of moving object
If shield electrode dimensions are reduced due to shrinking semiconductor dimensions, then device scaling is achieved, but shield resistance increases
Solution Approach 1:
The patent applies local quality by implementing a non-uniform doping profile where specific portions of the semiconductor mesa have enhanced doping concentrations. This localized electrical property optimization compensates for the increased resistance caused by reduced shield electrode dimensions, enabling device scaling while maintaining low shield resistance.
Solution Approach 2:
The patent changes the doping concentration parameter in specific regions of the semiconductor mesa to compensate for the effects of dimension reduction. By adjusting this material parameter locally, the patent maintains low shield resistance even as overall device dimensions shrink.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for low shield and gate resistance while maintaining high breakdown voltage, improving gate bounce and unclamped inductive switching performance without increasing die size or complicating packaging.
Implementation Method 1
a proximal end portion having a first doping concentration of the first conductivity type; a distal end portion having the first doping concentration of the first conductivity type; and a central portion disposed between the proximal end portion and the distal end portion, the central portion having a second doping concentration of the first conductivity type
Data Source
AI summary
In a general aspect, a vertical transistor can include a semiconductor region of a first conductivity type, and a plurality of perpendicularly intersecting trenches having a shielded gate structure of the vertical transistor disposed therein. A mesa of the semiconductor region can be defined by the plurality of perpendicularly intersecting trenches. The mesa can include a proximal end portion having a first doping concentration of the first conductivity type, a distal end portion having the first doping concentration of the first conductivity type, and a central portion disposed between the proximal end portion and the distal end portion. The central portion can have a second doping concentration of the first conductivity type that is less than the first doping concentration.