Vertical Trench SiC JFET With Capacitive Floating-Gate Control
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Solution Overview
Problem
Conventional silicon carbide-based junction field effect transistors (JFETs) face limitations due to gate electrodes that cannot withstand high voltages and have low reliability, which restrict their application as power switches, along with issues related to low mobility and poor performance caused by conducting channels near the material surface and poor quality of gate dielectric layers.
Innovation Solution
A vertical trench coupling capacitance gate-controlled junction field effect transistor design featuring a substrate, epitaxial layer, and repeating units with a floating gate controlled indirectly by a coupling capacitance upper electrode through a dielectric layer, allowing higher voltage application without conducting and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate electrode structure is used in SiC JFET, then the device structure is simple, but the gate electrode cannot withstand high voltages and has low reliability
Solution Approach 1:
The gate structure is segmented into multiple functional layers: a first gate electrode (P-type) forming a PN junction with the channel, and a second gate electrode (N-type) forming a second PN junction, with a dielectric layer between them. This segmentation allows each layer to handle specific voltage ranges and functions, enabling the overall gate structure to withstand high voltages while maintaining reliability.
Solution Approach 2:
The gate structure employs a nested configuration where the first gate electrode and second gate electrode are positioned at different depths within the epitaxial layer, with the dielectric layer nested between them. This nested arrangement creates multiple PN junctions at different levels, allowing the structure to block high voltages through series connection of multiple junctions while maintaining a compact form factor.
2Reliability
If the conducting channel is located inside the semiconductor material, then surface mobility issues are avoided, but the device becomes a normally-on device requiring gate voltage to turn off
Solution Approach 1:
The dual-gate structure enables dynamic control of the channel conduction state through coordinated voltage application to both gate electrodes. By applying appropriate voltages to the first and second gate electrodes, the PN junctions can be forward or reverse biased to control channel conductivity, allowing flexible switching between normally-on and normally-off modes of operation.
Solution Approach 2:
The invention changes the electrical parameters (doping concentrations, junction depths, dielectric properties) of the gate structure to achieve desired threshold voltages and conduction characteristics. By adjusting these parameters, the device can be designed to operate as normally-on or normally-off, providing adaptability for different application requirements while maintaining reliable internal channel conduction.
3Reliability
If a P+ type gate layer forms a PN junction with the channel, then the JFET operates as intended, but a voltage higher than 3V cannot be applied to the gate electrode
Solution Approach 1:
The gate structure employs a nested configuration where the first gate electrode (P-type) and second gate electrode (N-type) are positioned at different depths within the epitaxial layer, with a dielectric layer nested between them. This nested arrangement creates multiple PN junctions at different levels, allowing the structure to block high voltages through series connection of multiple junctions.
Solution Approach 2:
The gate structure is segmented into multiple functional layers: a first gate electrode (P-type) forming a PN junction with the channel, and a second gate electrode (N-type) forming a second PN junction, with a dielectric layer between them. This segmentation allows each layer to handle specific voltage ranges and functions, enabling the overall gate structure to withstand high voltages while maintaining reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enables the transistor to operate reliably at high voltages without affecting current characteristics, improves carrier mobility, and reduces conducting resistance, making it suitable for power switch applications.
Implementation Method 1
a coupling capacitance upper electrode, formed on the dielectric layer... The gate is indirectly controlled by the coupling capacitance upper electrode spaced with the dielectric layer
Data Source
AI summary
Disclosed are a vertical trench coupling capacitance gate-controlled junction field effect transistor and a manufacturing method thereof. The vertical trench coupling capacitance gate-controlled junction field effect transistor includes a substrate of a first doping type, an epitaxial layer of the first doping type, and a plurality of repeating units disposed adjacently; where the epitaxial layer is disposed on the substrate, the substrate is served as a drain region, and each of the repeating units includes: two source regions of the first doping type; a trench; a gate of the second doping type; a dielectric; and a coupling capacitance upper electrode, where the gate is indirectly controlled by the coupling capacitance upper electrode spaced with the dielectric layer.