Clocked Vertical Unipolar Logic Gates for Low Stand-By Power
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Solution Overview
Problem
Conventional unipolar logic circuits face high stand-by power issues, limiting their large-scale adoption in the electronics industry, despite advancements in semiconductor materials like thin film amorphous metal oxides and compound semiconductors, which are mainly implemented as NMOS or PMOS but not both, necessitating a new circuit design for low stand-by power and high-speed performance.
Innovation Solution
The development of novel unipolar circuits with vertical structures that employ capacitors for precharge and bootstrap operations, clocked gate designs, and ultra-short transistor channel lengths fabricated through deposition processes, enabling low power consumption and high-speed operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If unipolar logic circuits are used to reduce manufacturing cost, then manufacturing cost is reduced, but stand-by power increases
Solution Approach 1:
The patent applies precharge operations using capacitors to prepare the circuit state before actual logic operation. Capacitors are charged during precharge phases to store energy, eliminating the need for continuous power supply during stand-by periods. This preliminary action of charging capacitors before operation reduces stand-by power consumption while maintaining unipolar logic's manufacturing cost advantage.
Solution Approach 2:
The patent implements periodic clocked operations where capacitors are charged and discharged in cycles rather than maintaining continuous power flow. The clock signal controls periodic evaluation phases where logic operations occur, followed by stand-by phases where power consumption is minimized. This periodic action pattern reduces average stand-by power while keeping manufacturing costs low.
2Device complexity
If conventional unipolar logic is used to simplify circuit design, then device complexity is reduced, but stand-by power increases
Solution Approach 1:
The patent introduces precharge operations that prepare capacitor states before logic evaluation. This preliminary action maintains relatively simple unipolar circuit structures while reducing stand-by power, as capacitors hold charge during stand-by periods without requiring continuous power supply to maintain logic states.
Solution Approach 2:
The patent uses capacitors as intermediary energy storage elements between the power supply and logic gates. These capacitors mediate the power delivery, storing energy during precharge phases and releasing it during evaluation phases, thereby reducing stand-by power consumption while maintaining simple unipolar circuit design.
3Speed
If ultra-short transistor channel lengths are used to increase speed, then operation speed is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent transitions from planar transistor structures to vertical transistor structures. This dimensional change allows achieving ultra-short effective channel lengths through vertical stacking rather than lateral scaling. The vertical orientation enables precise control of channel length through deposition thickness control, which is more achievable with standard manufacturing processes, thereby achieving high speed operation without excessive precision requirements.
Solution Approach 2:
The patent changes the geometric parameters of transistor channels from lateral dimensions to vertical dimensions. By controlling the vertical thickness of semiconductor layers through deposition processes, ultra-short channel lengths are achieved with precision controlled by deposition techniques rather than lithography, relaxing manufacturing precision requirements while maintaining high operation speed.
4Quantity of substance
If vertical structures are used to increase density, then circuit density is improved, but device complexity increases
Solution Approach 1:
The patent employs vertical stacking of transistor layers to achieve high circuit density in the vertical dimension rather than expanding horizontally. This dimensional transition allows multiple logic gates to be stacked vertically, increasing the quantity of circuit elements per unit area while using standardized vertical fabrication processes, thereby managing complexity through process standardization.
Solution Approach 2:
The vertical structure design uses universal building blocks that can be stacked and combined to form different logic functions. The same vertical transistor layer structure serves multiple logic gates, and interconnect layers are designed to handle multiple signals simultaneously. This multi-functionality approach increases circuit density while managing complexity through modular, reusable design elements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
These designs achieve low stand-by power, high-speed performance, and increased density compared to conventional silicon CMOS circuitry, facilitating the integration of new transistor materials into large-scale electronics.
Implementation Method 1
capacitors are employed to enable a precharge state. In another embodiment, capacitors are employed in a bootstrap fashion to maintain the integrity of the high voltage gate output
Implementation Method 2
Ultra-short transistor channel lengths in vertical unipolar logic gates are fabricated with a deposition process
Data Source
AI summary
Novel unipolar circuits and vertical structures are described which exhibit low stand-by power, low dynamic power, high speed performance, and have higher density compared to conventional silicon CMOS circuitry. In one embodiment, a design methodology utilizing either a p-channel or n-channel transistor type such that each logic gate is clocked and the clocking mechanism provides the pull up or pull down. Further embodiments include novel designs of vertical unipolar logic gates which provides for high density. Ultra-short transistor channel lengths in vertical unipolar logic gates are fabricated with a deposition process—in lieu of a lithography process—thereby providing for high speed operation and low cost manufacturing.