Vertical Utility Patch Layout for Dense Semiconductor Power Delivery
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Solution Overview
Problem
Current power delivery and routing technologies for semiconductor packages face limitations such as low efficiency, high transient times, challenging fabrication processes, and large size requirements, which hinder scalability and integration in applications like integrated power systems.
Innovation Solution
The implementation of a customizable embedded utility patch with vertically oriented inductor, capacitor, and conductive trace structures within a package substrate, allowing for higher routing density and efficient power delivery, utilizing laminated patch substrates with magnetic inductor and capacitor structures rotated vertically to enhance power efficiency and reduce footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional power delivery technologies are used, then ease of manufacture is improved, but power efficiency deteriorates
Solution Approach 1:
The patent transitions from planar (2D) power delivery routing to three-dimensional (3D) vertically embedded utility patches. By stacking multiple substrate layers and creating vertical interconnects, the invention achieves higher power efficiency through reduced current path lengths and improved thermal management, while maintaining manufacturability through standard semiconductor fabrication processes adapted for 3D integration.
Solution Approach 2:
The invention embeds utility patches (containing power delivery components) within the internal structure of the semiconductor package substrate. Multiple functional layers are nested vertically, with conductive traces, vias, and embedded components stacked in three dimensions, allowing efficient power delivery without increasing the package footprint.
2Loss of energy
If high efficiency power delivery technologies are used, then power efficiency is improved, but transient time increases
Solution Approach 1:
The utility patches are strategically positioned in specific locations within the substrate to optimize local power delivery characteristics. By placing power delivery components close to their points of use and creating localized high-efficiency pathways, the invention reduces both energy loss and the time required for power transient responses.
3Ease of manufacture
If current routing technologies are used, then ease of manufacture is improved, but package size increases
Solution Approach 1:
The invention moves from two-dimensional planar routing to three-dimensional vertical embedding. Conductive traces and utility patches are stacked across multiple substrate layers, allowing power and signal routing to occur in the vertical dimension. This dramatically reduces the horizontal footprint and overall package size while maintaining ease of manufacture through adapted fabrication processes.
4Loss of energy
If vertically embedded utility patches are implemented, then power efficiency is improved, but device complexity increases
Solution Approach 1:
The invention divides the power delivery system into discrete, modular utility patches that can be independently designed, fabricated, and integrated. Each patch contains specific functional elements (conductive traces, vias, embedded components) that can be optimized separately. This segmentation reduces overall device complexity by breaking down the complex 3D integration problem into manageable modular units.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves high power efficiency, low transient times, and smaller footprints while supporting higher routing densities and lower costs, enabling integration in various electronic devices.
Implementation Method 1
customizable embedded utility patch with vertically oriented inductor, capacitor, and conductive trace structures
Implementation Method 2
customizable embedded utility patch with vertically oriented inductor, capacitor, and conductive trace structures
Implementation Method 3
conductive trace structures within a package substrate, allowing for higher routing density and efficient power delivery
Data Source
AI summary
Integrated circuit (IC) devices and systems with embedded utility patches, and methods of forming the same, are disclosed herein. In one embodiment, a microelectronic assembly includes a first substrate with a cavity, and one or more second substrates embedded in the cavity. The first substrate is oriented on a first plane, and the one or more second substrates are oriented on one or more second planes that are substantially orthogonal to the first plane.