Vertical Vacuum Transistor Air Gap Minimization
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Solution Overview
Problem
The formation of parasitic capacitance between conductive structures in integrated circuits due to dielectric layers leads to increased RC delay and decreased device operating speed, necessitating a method to minimize air gaps between the gate and tip in semiconductor devices.
Innovation Solution
A method involving the formation of air gaps within a fin stack using epitaxial growths, where a hardmask and dielectric layers are deposited and etched to create a cavity, allowing for the growth of triangle-shaped epitaxial structures that minimize the gap between the gate and tip, thereby controlling the electric field effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dielectric layers are used to cover substrate and transistor after transistor manufacturing, then device isolation is achieved, but parasitic capacitance between gate and source/drain region increases
Solution Approach 1:
The patent extracts the harmful dielectric material between the gate and source/drain regions by forming air gaps in these specific locations. The dielectric layer is selectively removed to create vacuum/air regions that eliminate parasitic capacitance while preserving the dielectric layer in areas where isolation is needed.
Solution Approach 2:
The patent applies different material properties to different locations: air/vacuum is introduced specifically between the gate and source/drain regions to reduce capacitance, while dielectric material is maintained in other areas for isolation purposes. This localized modification optimizes the electrical characteristics without compromising overall device isolation.
2Productivity
If parasitic capacitance between conductive structures is reduced by minimizing air gaps, then RC delay decreases and device operating speed increases, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming the air gaps and epitaxial growths before final transistor completion. The air gaps are created and the epitaxial structures are grown in advance, which simplifies subsequent processing steps and integrates the capacitance reduction feature into the existing manufacturing flow.
Solution Approach 2:
The patent introduces epitaxial growths as intermediary structures that fill the air gaps and provide a bridge between the gate and source/drain regions. These epitaxial structures serve as mediators that maintain mechanical support and electrical isolation while preserving the low-capacitance air gap environment, thus enabling complex functionality without proportionally increasing manufacturing difficulty.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic capacitance, enhances gate control efficiency, and enables the creation of vacuum channel transistors capable of operating at terahertz frequencies while maintaining compatibility with advanced CMOS technology nodes like 5-7 nm vertical CMOS technology.
Implementation Method 1
forming triangle-shaped epitaxial growths within the air gap defined within the fin stack
Data Source
AI summary
A method is presented for controlling an electric field from a gate structure. The method includes forming a hardmask over a fin stack including a plurality of layers, forming a first dielectric layer over the hardmask, forming a sacrificial layer over the first dielectric layer, etching the sacrificial layer to expose a top surface of the first dielectric layer, depositing a second dielectric layer in direct contact with exposed surfaces of the first dielectric layer and the sacrificial layer, removing a layer of the plurality of layers of the fin stack to define an air gap within the fin stack, and forming triangle-shaped epitaxial growths within the air gap defined within the fin stack.