Vertical Variable Resistance Memory Device for High Integration Density
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Solution Overview
Problem
Modern semiconductor devices face limitations in integration due to the need for expensive equipment to reduce feature sizes in two-dimensional devices, and there is a demand for high-performance, low-power semiconductor memory devices that current technologies struggle to meet.
Innovation Solution
A variable resistance memory device with a vertical structure that includes a vertical conductive line, a variable resistance element, and a selection element, stacked on a substrate with horizontal conductive lines, allowing for three-dimensional arrangement and efficient data storage using materials like GeTe and GeSe, enabling controlled resistance values through crystallization changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional planar semiconductor devices are used, then manufacturing process is simpler, but integration density is limited due to area occupation
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically-stacked memory cells. Multiple memory cell layers are stacked in the vertical direction (first direction perpendicular to substrate), with each layer containing bit lines, word lines, and memory elements arranged vertically. This dimensional transition dramatically increases integration density without requiring proportionally smaller feature sizes, thereby improving storage capacity while maintaining manufacturability.
2Quantity of substance
If feature size is reduced to increase integration in two-dimensional devices, then integration density improves, but expensive equipment is required
Solution Approach 1:
Instead of continuing to reduce feature sizes in the planar direction (which would require increasingly expensive lithography equipment), the patent stacks multiple memory cell layers vertically. This allows integration density to increase by utilizing the third dimension (vertical stacking) rather than continuously shrinking horizontal features, thereby avoiding the need for extremely expensive next-generation lithography equipment while achieving higher density.
Solution Approach 2:
The patent employs a nested structure where multiple memory cell layers are stacked one on top of another, with each layer containing conductive lines and memory elements that are vertically aligned or offset. The bit lines, word lines, and memory elements of different layers are nested in the vertical space, allowing high integration density without requiring proportional reduction in feature sizes, thus avoiding expensive equipment requirements.
3Ease of manufacture
If conventional memory technologies are used, then current manufacturing capabilities are sufficient, but power consumption is high and performance is limited
Solution Approach 1:
The patent employs composite material structures for the memory elements, including phase-change materials (such as GeTe, GeSe, or GST alloys) that can transition between crystalline and amorphous phases. These composite material structures enable lower operating voltages and reduced power consumption compared to conventional memory technologies, while maintaining compatibility with existing semiconductor manufacturing processes. The phase-change materials allow for energy-efficient data storage through controlled phase transitions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances integration density and power efficiency in semiconductor memory devices by allowing for vertical stacking and controlled resistance values, addressing the limitations of two-dimensional devices and meeting the demand for high-performance, low-power memory solutions.
Implementation Method 1
enabling controlled resistance values through crystallization changes
Data Source
AI summary
A variable resistance memory device includes a stacking pattern disposed on a substrate, a vertical structure extends in a first direction, which is perpendicular to a top surface of the substrate, and penetrates the stacking pattern, and a horizontal conductive line disposed adjacent to the stacking pattern and extending in a second direction that is parallel to the top surface of the substrate. The vertical structure includes a vertical conductive line penetrating the stacking pattern, a variable resistance element enclosing the vertical conductive line, and a selection element interposed between the vertical conductive line and the variable resistance element. Each of the vertical conductive line, the variable resistance element, and the selection element extends in the first direction. The stacking pattern is electrically connected to the horizontal conductive line and extends along the horizontal conductive line and in the second direction.