Vertical DRAM VFET Structure for Higher Cell Integration Density
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Solution Overview
Problem
The complexity of manufacturing and integration in dynamic random access memories (DRAMs) leads to deficiencies and reduced performance, as the shrinking dimensions of memory cells increase complexity, necessitating improved structural and manufacturing processes to enhance packing densities and performance.
Innovation Solution
A memory device with a vertical field effect transistor (VFET) is developed, featuring a channel structure electrically connected to both a capacitor and a bit line through direct contacts, and gate structures on opposite sidewalls, allowing for increased integration density by reducing the surface area occupied by components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional planar transistor structures are used in DRAM, then manufacturing processes are relatively simple, but integration density and packing density are limited
Solution Approach 1:
The patent transitions from a planar (2D) transistor structure to a vertical field effect transistor (VFET) structure that utilizes the third dimension (vertical direction). The channel structure extends vertically from the semiconductor substrate, with gate structures wrapping around the channel from multiple directions. This dimensional change allows for increased integration density while maintaining manufacturability, as the vertical architecture reduces the horizontal footprint of each memory cell without requiring excessively complex manufacturing processes.
2Area of stationary object
If continuous shrinkage of DRAM cell dimensions is pursued to increase packing density, then more memory cells fit per chip area, but manufacturing and integration complexity increases significantly
Solution Approach 1:
Instead of continuously shrinking horizontal dimensions which exponentially increases manufacturing complexity, the patent employs vertical channel structures that extend in the Z-direction. This allows memory cells to maintain larger horizontal dimensions for easier manufacturing while achieving higher packing density through vertical stacking. The gate structures wrap around the vertical channel, providing effective control without requiring sub-10nm lithography processes.
Solution Approach 2:
The VFET structure segments the transistor into distinct vertical components: the channel structure extending from the substrate, gate structures positioned at different heights and angles, and separate capacitor and bit line contacts. This segmentation allows each component to be optimized independently and facilitates modular manufacturing approaches, reducing overall integration complexity while achieving high density.
3Area of stationary object
If vertical field effect transistor structure is implemented, then integration density is enhanced, but device structure becomes more complex
Solution Approach 1:
The patent implements a vertical field effect transistor where the channel structure extends vertically from the semiconductor substrate surface. Gate structures are positioned at different vertical levels and wrap around the channel from multiple directions (e.g., first gate structure from one side, second gate structure from the opposite side). This vertical architecture achieves high integration density by utilizing the third dimension, while the systematic arrangement of components reduces structural complexity compared to alternative 3D configurations.
Solution Approach 2:
The VFET structure employs asymmetric gate positioning where gate structures are located at different vertical heights and angular positions around the vertical channel. This asymmetric arrangement optimizes the electric field distribution for effective channel control while allowing simplified fabrication processes. The capacitor and bit line contacts are also positioned asymmetrically to minimize interference and reduce overall device complexity.
Data Source
AI summary
The present disclosure relates to a memory device with a vertical field effect transistor (VFET) and a method for preparing the memory device. The memory device includes a capacitor contact disposed in a first semiconductor substrate, and a channel structure disposed over a top surface of the first semiconductor substrate. The memory device also includes a first gate structure disposed on a first sidewall of the channel structure, and a second gate structure disposed on a second sidewall of the channel structure. The second sidewall of the channel structure is opposite to the first sidewall of the channel structure. The memory device further includes a bit line contact disposed over the channel structure. The channel structure is electrically connected to a capacitor and a bit line through the capacitor contact and the bit line contact.