Vertical-Through-Via Connector for 3D Chip Signal and Power Routing
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Solution Overview
Problem
Current chip packaging technologies face challenges in efficiently transmitting signals and delivering power/ground in a vertical fashion as semiconductor integrated-circuit (IC) chips are scaled down, requiring innovative interconnection solutions to maintain performance and efficiency.
Innovation Solution
A vertical-through-via connector is developed using a glass substrate with interconnection metal layers acting as vertical through vias, enabling signal transmission and power/ground delivery in a vertical fashion by forming multiple metal traces and vias that connect the substrate surfaces, allowing for efficient communication between IC chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor IC chips are arranged in a two-dimensional plane on a circuit substrate, then signal transmission and power delivery can be achieved using metal traces, but the package size cannot be scaled down further
Solution Approach 1:
The patent transitions from two-dimensional planar arrangement of IC chips to three-dimensional vertical stacking configuration. Metal traces are extended vertically through the substrate to connect chips at different height levels, enabling spatial utilization in the vertical dimension while maintaining signal transmission efficiency.
Solution Approach 2:
The circuit substrate is divided into multiple segments or layers with individual IC chips mounted on each segment. Vertical metal traces act as interconnectors between these segmented layers, allowing independent optimization of each layer while maintaining overall system functionality.
2Volume of moving object
If IC chips are arranged vertically to reduce package size, then volume is reduced, but new interconnection structures are required for signal transmission
Solution Approach 1:
The vertical metal traces serve multiple functions: they act as mechanical support structures for stacking chips, provide electrical interconnection between layers, and enable both signal transmission and power delivery. This multi-functionality reduces the need for separate dedicated interconnection components.
Solution Approach 2:
The patent combines the substrate structure with interconnection functions by integrating vertical metal traces directly into the substrate architecture. This merging of structural and interconnection functions simplifies the overall device complexity compared to using separate mechanical supports and electrical interconnectors.
Data Source
AI summary
A connector may include: a first substrate having a top surface, a bottom surface opposite to the top surface of the top substrate and a side surface joining an edge of the top surface of the first substrate and joining an edge of the bottom surface of the first substrate; a second substrate having a top surface, a bottom surface opposite to the top surface of the second substrate and a side surface joining an edge of the top surface of the second substrate and joining an edge of the bottom surface of the second substrate, wherein the side surface of the second substrate faces the side surface of the first substrate, wherein the top surfaces of the first and second substrates are coplanar with each other at a top of the connector and the bottom surfaces of the first and second substrates are coplanar with each other at a bottom of the connector; and a plurality of metal traces between, in a first horizontal direction, the side surfaces of the first and second substrates, wherein each of the plurality of metal traces has a top end at the top of the connector and a bottom end at the bottom of the connector.