Semiconductor Package Vertical Via Layout for Current Redistribution
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Solution Overview
Problem
Existing semiconductor packages face challenges in efficiently redistributing current and managing thermal performance due to uniform distribution of conductive vias, which can lead to under-loaded vias and increased manufacturing costs.
Innovation Solution
The semiconductor package incorporates a vertical redistribution structure with multiple substantially parallel vertical paths arranged non-uniformly over a contact pad, allowing for selective depopulation of vias to create via-free zones, thereby optimizing current distribution and reducing the number of vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If uniform distribution of conductive vias is used, then current redistribution is achieved, but manufacturing complexity and material usage increase
Solution Approach 1:
The patent extracts and removes certain vias from the uniform distribution pattern to create via-free zones. This selective removal reduces the total number of vias and associated materials while maintaining current redistribution functionality through the remaining strategically positioned vias.
Solution Approach 2:
The patent applies local quality by creating non-uniform via distribution with via-free zones in specific regions. Different areas of the contact pad have different via densities, optimizing current flow paths and reducing material usage in regions where vias are less critical for current redistribution.
2Quantity of substance
If non-uniform via distribution with via-free zones is implemented, then material usage is reduced, but current density distribution must be precisely controlled
Solution Approach 1:
The patent performs preliminary simulation and analysis of current density distribution before finalizing the via layout. This preliminary action allows optimization of via placement to ensure acceptable current density control in the non-uniform distribution, avoiding the need for complex real-time control during manufacturing.
3Ease of manufacture
If selective depopulation of vias is performed, then manufacturing cost is reduced, but electrical performance must be maintained within tolerance
Solution Approach 1:
The patent incorporates feedback mechanisms through simulation and analysis of current density distribution to verify that selective via depopulation maintains electrical performance within tolerance. This feedback loop allows optimization of via removal while ensuring reliability requirements are met.
Data Source
AI summary
In an embodiment, a method for fabricating a semiconductor package includes: embedding a semiconductor device in an insulating layer; forming a contact pad having an area that does not overlap the semiconductor device; and forming a vertical current redistribution structure that includes substantially parallel vertical current paths arranged in the insulating layer and extending perpendicular to the area of the contact pad that does not overlap the semiconductor device. The substantially parallel vertical current paths are non-uniformly distributed over the area of the contact pad that does not overlap the semiconductor device.