Vertical Via Etching for LED Contact Reliability
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Solution Overview
Problem
Existing semiconductor light emitting devices face issues with reliability and performance due to damage from plasma-ion etching and contamination on sloped via walls, leading to current leakage and optical loss.
Innovation Solution
The fabrication method involves creating vertical vias with orthogonal walls to reduce plasma-induced damage and contamination, using dielectric structures to provide a continuous slope for metal contact, and applying a reflective layer to maximize light reflection without vertical drops, which enhances the contact area and reduces the risk of gaps or cracks in the metal layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If plasma-ion isotropic etching is used to create vias with sloped walls, then the via walls facilitate metal layer application, but the sloped walls cause active layer damage and contamination leading to current leakage
Solution Approach 1:
The patent inverts the conventional via wall orientation by creating vertical walls instead of sloped walls. This is achieved through anisotropic etching processes that produce substantially vertical via walls, fundamentally changing the geometry to eliminate the root cause of plasma damage and contamination accumulation that leads to current leakage
Solution Approach 2:
The patent changes the etching process parameters from isotropic to anisotropic conditions, transforming the via wall angle from sloped to substantially vertical. This parameter change in the etching process directly addresses the contradiction by maintaining manufacturability while eliminating reliability issues
2Illumination intensity
If the reflective layer extends to the via edge to maximize reflective surface area, then light reflection is improved, but vertical drops in metal layer are created causing gaps or cracks
Solution Approach 1:
The patent inverts the conventional approach by creating vertical via walls instead of sloped walls. This geometric inversion eliminates the vertical drop issue at the via edge, allowing the reflective layer to extend to the via edge without creating metal layer defects, thus maintaining both light reflection and metal layer integrity
3Illumination intensity
If via opening size is reduced to maximize reflective layer area, then optical loss is reduced, but contact area with N-type layer and separation from active layer become insufficient
Solution Approach 1:
The patent transitions from horizontal area optimization to vertical dimension utilization by creating substantially vertical via walls. This dimensional change allows the via to maintain a smaller opening size while providing sufficient contact area with the N-type layer through the vertical extent, and adequate separation from the active layer, thus resolving the contradiction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the reliability and performance of light emitting devices by minimizing damage to the active layer, reducing current leakage, and increasing the reflective surface area, resulting in improved light output and extended device lifespan.
Implementation Method 1
Plasma-Ion isotropic etching 190 is commonly used to produce sloped via walls 185 within the via 180
Implementation Method 2
This reflective layer 150 redirects light toward the N-type semiconductor layer 120, reducing the likelihood of optical loss due to absorption within the light emitting device
Data Source
Figure 1A~1D
Figure 2A~2F
Figure 3
AI summary
A light emitting device includes a vertical via through the P-type semiconductor layer and the active layer. Using a vertical via reduces quantum well damage, allows shortening of P-N spacing, and allows increased reflective area. A dielectric structure is formed in the via to provide a sloped wall that extends to an upper surface of the device. Another dielectric layer covers the upper surface and the sloped wall, and provides select contacts to the semiconductor layers. A metal layer is subsequently applied. Because the dielectric layers provide a continuous slope from the surface of the device, the metal layer does not include a vertical drop. Because the active layer does not extend into the via, the contact to the N-type semiconductor layer may be situated closer to the wall of the via, increasing the area available for a reflective layer.