Vertical Interconnect Via Structure for Low-Loss Millimeter-Wave PCBs

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Solution Overview

Problem

Conventional vertical interconnection structures in multi-layer substrates exhibit strong capacitive behavior due to dielectric loading, leading to mismatch and increased insertion loss at high frequencies, limiting their effectiveness in high-frequency and millimeter-wave applications.

Innovation Solution

A vertical interconnection structure is designed with non-circular signal and ground vias, and ring-type ground vias surrounding non-circular signal vias, which reduces capacitive coupling and enhances electromagnetic interference shielding, allowing for improved signal transmission without additional matching components.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional vertical interconnection structures are used in multi-layer substrates, then the structure is simple and easy to manufacture, but strong capacitive behavior occurs due to dielectric loading, causing mismatch and increased insertion loss at high frequencies

Engineering Contradiction:
Improvesignal transmission qualityVSAvoidvia structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies asymmetry by using non-circular via structures (such as rectangular or oval shapes) instead of conventional circular vias. This asymmetric geometry reduces the capacitive coupling between adjacent vias and between vias and ground planes, thereby reducing mismatch and insertion loss at high frequencies while maintaining manufacturing feasibility through standard PCB drilling and plating processes

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent introduces dimensionality change by adding ring-type ground vias surrounding the signal vias, creating a multi-dimensional interconnection structure. This additional dimensional arrangement (signal via surrounded by ground rings) provides EMI shielding and controls electromagnetic fields without significantly increasing manufacturing complexity, as it uses the same via formation processes arranged in different spatial configurations

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If conventional circular vias are used, then the manufacturing process is simple, but capacitive coupling is strong leading to mismatch at high frequencies

Engineering Contradiction:
Improvevia fabrication easeVSAvoidsignal integrity precision
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent changes the via cross-sectional shape from circular to non-circular (rectangular, oval, or other polygons). This asymmetric shape reduces the overlap area between electric fields of adjacent vias, thereby reducing capacitive coupling and improving signal integrity precision. The non-circular shapes can still be manufactured using standard PCB processes with appropriate tooling and plating optimization

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent modifies geometric parameters of the via structures, including shape (circular to non-circular), size (diameter or equivalent dimensions), and spacing. By optimizing these parameters, the capacitive effects are reduced while maintaining compatibility with standard manufacturing capabilities, achieving better signal integrity without requiring entirely new fabrication processes

Inventive Principle:
Principle #35Parameter changes

3Reliability

If additional matching components are added to reduce capacitive effects, then signal transmission quality improves, but device complexity and cost increase

Engineering Contradiction:
Improvesignal transmission qualityVSAvoidinterconnection structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the capacitive matching function from separate discrete components and integrates it directly into the via structure itself. By designing the via geometry (non-circular shapes, ring configurations) to inherently reduce capacitive effects, the matching function is built into the interconnection structure, eliminating the need for additional matching components and reducing overall device complexity

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent makes the via structure multi-functional by designing it to simultaneously serve as the interconnection pathway and the capacitive matching element. The non-circular via geometry and surrounding ground rings perform both the signal transmission function and the capacitive compensation function, reducing the need for separate matching components and simplifying the overall device structure

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design achieves a 10-30 dB bandwidth improvement for voltage standing wave ratio (VSWR) at 1.2:1 within a frequency span of 15-50 GHz, suitable for high-frequency applications like 5G, by reducing capacitive effects and enhancing EMI shielding.

Implementation Method 1

ring-type ground vias surrounding non-circular signal vias, which reduces capacitive coupling and enhances electromagnetic interference shielding

Methodology Applied
Scientific EffectElectromagnetic shielding: Faraday Cage

Data Source

PatentEP3828924B1Vertical interconnection structure of a multi-layer substrate
Publication Date: 2025.01.01 MEDIATEK INC
  • EP3828924B1 patent drawingFigure 1~2
  • EP3828924B1 patent drawingFigure 3~5
  • EP3828924B1 patent drawingFigure 6~7

AI summary

A vertical interconnection structure (VI) of a multi-layer substrate (10) includes a first via pad (VP3) disposed in a first layer of metal interconnect (L3) of the multi-layer substrate (10); a second via pad (VP2) disposed in a second layer of metal interconnect (L2) of the multi-layer substrate (10); a signal via (SV3) electrically connecting the first via pad (VP3) to the second via pad (VP2); a non-circular first ground plane (GL3) disposed in the first layer of metal interconnect (L3) of the multi-layer substrate (10) and surrounding the first via pad (VP3); and a non-circular first ground pullback region (GP3) between the first via pad (VP3) and the non-circular first ground plane (GL3) for electrically isolating the first via pad (VP3) from the non-circular first ground plane (GL3).