Vertical Via PCM Structure for BEOL Memory Integration
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Solution Overview
Problem
The challenge of miniaturizing semiconductor chip designs is hindered by limitations in metallization layer design, leading to difficulties in achieving further miniaturization goals due to conflicts between design requirements and layout restrictions, particularly in integrating memory elements efficiently within semiconductor stacks.
Innovation Solution
The integration of a phase change material non-volatile memory (PCM) within vertical vias interconnecting BEOL metallization layers, utilizing a novel fabrication process that includes tapered vertical via structures and efficient deposition methods to form electrical connections between metallization contacts, allowing for the integration of memory elements in a single exposure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device features are located closer to each other to increase feature density, then chip design capability is improved, but metallization layer design limitations worsen due to smaller wire widths and tighter pitch tolerances
Solution Approach 1:
The patent transitions from planar metallization interconnections to three-dimensional vertical vias that extend through multiple metallization layers. This dimensional change allows signals to travel vertically through the stack rather than laterally across the chip surface, enabling closer horizontal spacing of device features while maintaining reliable electrical connections without being constrained by lateral pitch tolerances
Solution Approach 2:
The patent embeds memory elements (such as phase change material layers) within the vertical via structures that interconnect metallization layers. This nesting approach integrates memory functionality directly into the interconnection architecture, maximizing space utilization and enabling higher feature density without requiring separate dedicated memory regions that would consume valuable lateral chip real estate
2Productivity
If new fabrication process elements are introduced to resolve metallization limitations, then miniaturization capability is improved, but device complexity increases
Solution Approach 1:
The patent designs vertical via structures that simultaneously serve multiple functions: providing electrical interconnections between metallization layers, hosting memory elements for data storage, and establishing thermal pathways. This multi-functionality reduces the need for separate dedicated structures for each function, thereby limiting the increase in overall device complexity while enabling advanced miniaturization
Solution Approach 2:
The patent combines interconnection and memory functions into a single integrated vertical via structure. By merging these previously separate functionalities into one unified architectural element, the patent achieves miniaturization benefits without proportionally increasing fabrication process complexity, as the combined structure can be formed through integrated process steps rather than separate sequential operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maximizes real estate utilization, reduces fabrication costs, and provides efficient electrical interconnections, addressing the inefficiencies of current semiconductor fabrication processes by integrating memory elements into vertical vias in BEOL metallization layers.
Implementation Method 1
a phase change material non-volatile memory (PCM) being vertically interposed between an upper electrode and a lower electrode
Implementation Method 2
A first vertical via interconnects, through the dielectric layer, the first and second metallization contacts
Data Source
AI summary
Various methods and structures for fabricating a semiconductor structure with vertical vias interconnecting BEOL metallization layers. A first BEOL metallization layer includes a first metallization contact. A second BEOL metallization layer is disposed on the first BEOL metallization layer. The second BEOL metallization layer includes a second metallization contact. A dielectric layer is vertically interposed between the first and second metallization layers. A first vertical via interconnects, through the dielectric layer, the first and second metallization contacts. In the first vertical via, a phase change material non-volatile memory (PCM) is vertically interposed between an upper electrode and a lower electrode. The lower electrode is electrically connected to the first metallization contact. The upper electrode is electrically connected to the second metallization contact.