Vertical Via Pin Standard Cells for Better Pin Access
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in integrated circuit (IC) fabrication is the limited accessibility and increased parasitic capacitance of long metal pins in standard cells, particularly at advanced nodes, which complicates pin access and affects performance and power due to tight design rules and reduced cell size.
Innovation Solution
Implementing vertical via pins in standard cells, which are perpendicular to the horizontal axis, allowing for improved pin accessibility, reduced metal usage, and simplified layout, thereby optimizing pin access and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If long metal pins are used in standard cells, then pin accessibility is improved, but parasitic capacitance increases and performance deteriorates
Solution Approach 1:
The patent transitions from horizontal metal pins to vertical via pins, changing the dimensional orientation of the connection structure. This vertical configuration reduces the horizontal footprint and parasitic capacitance while maintaining accessibility through the via structure that connects to upper metal layers.
Solution Approach 2:
The patent divides the pin structure into multiple segments: the via portion extending vertically from the standard cell and the metal pin portions in upper layers. This segmentation allows the via to provide vertical access while metal pins in upper layers provide horizontal connectivity, separating the accessibility function from the signaling function.
2Area of moving object
If standard cell size is reduced according to tight design rules, then integration density is improved, but pin accessibility deteriorates
Solution Approach 1:
By moving pin connections from the horizontal plane to the vertical dimension through via structures, the patent enables standard cells to maintain small footprint while achieving pin accessibility through the vertical via that extends above the cell boundary.
Solution Approach 2:
The via structure serves multiple functions: it provides vertical electrical connection, extends the pin access point above the standard cell for external connection, and reduces the horizontal space requirement within the standard cell, thereby supporting both miniaturization and accessibility.
3Object-generated harmful factors
If vertical via pins are implemented, then parasitic capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent merges the via formation process with the existing backend-of-line (BEOL) metal layer fabrication processes. The via pins are formed using the same deposition and patterning tools and processes already used for creating metal interconnect layers, thereby avoiding the need for separate specialized manufacturing equipment or processes.
Solution Approach 2:
The via structures are formed and prepared in advance during the BEOL fabrication sequence, before the final metal pin layers are deposited. This preliminary formation of via patterns and structures allows subsequent metal layers to be directly connected to the via pins using standard metal deposition processes, simplifying the overall manufacturing flow.
Data Source
AI summary
An IC device (e.g., a standard cell) may have one or more vertical via pins for power supply or signal transmission. The IC device may also include semiconductor structures stacked over each other along the vertical axis of the IC device and electrodes stacked over each other along the horizontal axis. An electrode may be a gate electrode over a channel region of a transistor or a trench electrode over a source region or drain region of a transistor. A vertical via pin may be connected to a gate electrode or trench electrode. A vertical via pin may be an input pin or output pin. A vertical via pin may have a longitudinal axis that is perpendicular or substantially perpendicular to the horizontal axis and the vertical axis of the IC device. The IC device may have an EEQ cell that includes cells having different layouts of vertical via pins.