Vertical Wafer Test Stack Layout for Shorter Signal Paths
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Solution Overview
Problem
Existing semiconductor wafer testing systems are large, inefficient, and face challenges in achieving minimal signal path lengths due to the need for probe cards and increasing test speeds.
Innovation Solution
A compact, modular system with vertical stacks of test engines and data buffers directly connected to the wafer contactor, eliminating probe cards and minimizing signal paths through direct connections to the wafer, utilizing cooling systems and fast data links.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If probe cards are used to interface pin driver boards to the wafer contactor, then electrical connections can be established, but the signal path length increases and device size becomes large
Solution Approach 1:
The patent extracts and eliminates the probe card from the testing system architecture. Instead of using a separate probe card component to interface pin driver boards to the wafer contactor, the system directly connects pin driver boards to the wafer contactor, removing the unnecessary intermediary element that increased signal path length and device complexity.
Solution Approach 2:
The patent merges the functions of the probe card and pin driver board into a direct connection architecture. By combining these previously separate components into a unified direct interface, the system reduces signal path length while maintaining electrical connection functionality.
2Productivity
If automated multi-site testing is implemented, then testing efficiency improves, but tester size becomes large
Solution Approach 1:
The patent transitions from a horizontal layout with probe cards extending across the wafer surface to a vertical stacking architecture where pin driver boards are stacked above the wafer contactor. This dimensional change allows multiple test sites to be arranged vertically, increasing testing efficiency while reducing the horizontal footprint and overall tester size.
Solution Approach 2:
The patent implements a nested architecture where pin driver boards are stacked vertically one above another in a compact arrangement. This nesting of test components in the vertical dimension enables multi-site testing capability while minimizing the horizontal space required, thus reducing overall tester size.
3Speed
If signal trace lengths are reduced to increase test speed, then testing speed improves, but system layout becomes more constrained
Solution Approach 1:
The patent resolves the layout constraint by moving the pin driver boards into the vertical dimension, stacking them above the wafer contactor. This vertical arrangement naturally minimizes signal trace lengths to the wafer surface while providing ample space for routing and connection, eliminating the trade-off between speed and layout complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system achieves high-performance, cost-effective testing with minimal signal trace lengths, enabling efficient and economical testing of semiconductor wafers and packaged devices.
Implementation Method 1
The cooling system includes a network of channels that pass a cooling fluid through the corner posts of the testing stacks to remove heat during operation.
Data Source
AI summary
The invention is a test system for testing silicon wafers or packaged devices. The system includes a tester having multiple testing stacks that each hold a vertical stack of test engines, data buffers, pin drivers, and other resources, which are electrically connected on one side to a wafer or DUT and on the other side to a test host computer via fast data links. Each testing stack is disposed on a top side of a wafer contactor electrically connected to a wafer or a load board electrically connected to a DUT. The system includes a cooling system to remove heat during operation. The system minimizes the data signal path between the pads of the devices being tested and the pin drivers of the tester, the test engines, and the test host computer. High performance is possible by the connection of bottom of each testing stack directly to the wafer contactor.