Vertical WLCSP Inductor Structure for Lower Die Coupling
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Solution Overview
Problem
Conventional planar inductors in semiconductor devices suffer from unwanted magnetic and capacitive coupling with the semiconductor die, leading to reduced quality factors and increased mechanical stress due to wirebonding, which is risky for fragile low-k dielectrics in modern chip technologies.
Innovation Solution
The implementation of vertically oriented inductors with conductive coils formed along a plane orthogonal to the semiconductor die surface, reducing magnetic flux penetration and capacitive coupling, and using redistribution layers and vias to integrate inductors into the package without increasing production costs or reducing throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If planar inductors are used in WLCSP packaging, then the inductors can be integrated into the package, but the magnetic flux lines penetrate into the semiconductor die surface causing eddy currents and reducing quality factor
Solution Approach 1:
The patent transitions from planar (2D) inductor geometry to a three-dimensional vertical structure. The conductive coil is formed above the semiconductor die surface using wirebonding techniques, creating a vertical inductor where the coil axis is perpendicular to the die surface. This dimensional change redirects magnetic flux away from the die surface, eliminating eddy current losses and improving quality factor.
2Reliability
If wirebonding techniques are used to form non-planar inductors, then magnetic flux penetration is reduced, but significant mechanical stress is applied to the semiconductor die surface
Solution Approach 1:
The patent performs wirebonding operations before final die assembly and packaging. By forming the vertical inductor structure on the die surface beforehand, the mechanical stress from wirebonding is applied when the die is still accessible and can be properly supported. This preliminary action prevents stress-related damage that would occur if wirebonding were attempted after die assembly.
3Adaptability or versatility
If wirebonding is performed on modern chips with low-k dielectrics, then non-planar inductors can be formed, but the risk of damaging the fragile BEOL-stack increases
Solution Approach 1:
The patent performs wirebonding operations before final die assembly and packaging. By forming the vertical inductor structure on the die surface beforehand, the mechanical stress from wirebonding is applied when the die is still accessible and can be properly supported. This preliminary action prevents stress-related damage that would occur if wirebonding were attempted after die assembly.
Solution Approach 2:
The patent introduces a support structure or carrier during the wirebonding process to distribute and reduce mechanical stress on the BEOL-stack. This intermediary element protects the fragile low-k dielectrics while allowing the wirebonding operation to proceed, thus enabling vertical inductor formation without compromising BEOL integrity.
4Reliability
If planar inductors are formed in packaging, then integration is achieved, but the conductive coil is located close to the die surface producing capacitive coupling
Solution Approach 1:
The patent transitions from planar (2D) inductor geometry to a three-dimensional vertical structure. The conductive coil is formed above the semiconductor die surface using wirebonding techniques, creating a vertical inductor where the coil axis is perpendicular to the die surface. This dimensional change redirects magnetic flux away from the die surface, eliminating eddy current losses and improving quality factor.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the quality factor of inductors by minimizing unwanted coupling and reduces mechanical stress on the die, while maintaining production efficiency and cost-effectiveness by leveraging existing processing operations for redistribution layers.
Implementation Method 1
the majority of the magnetic flux lines penetrate into the surface of the semiconductor die
Implementation Method 2
The magnetic flux lines formed by the inductor induce eddy currents that couple back to the inductor
Implementation Method 3
The close proximity of the conductive coil to the die surface produces undesirable capacitive coupling between the semiconductor die and the inductor
Data Source
AI summary
Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.