Vertically Aligned 2D Material Transistors for Miniaturization

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Solution Overview

Problem

Current semiconductor devices, such as transistors, face limitations in reducing size and increasing speed due to the flat structure of metal oxide semiconductor field effect transistors (MOSFETs), prompting the need for three-dimensional structures like fin field effect transistors (FinFETs), and there is a requirement for high-efficiency gas sensors with enhanced reactivity and reusability.

Innovation Solution

A two-dimensional (2D) material with a semiconductor having a 2D crystal structure is vertically aligned on a substrate, incorporating a transition metal dichalcogenide, with a gate insulation layer and gate electrode on the upper and side surfaces, and a method involving a guide pattern layer and chemical vapor deposition to form the 2D material, allowing for reduced contact resistance and high electron mobility, and a gas sensor design that can adsorb and release gases efficiently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If a flat structure MOSFET is used, then the device structure is simple, but the device size cannot be reduced further and drive speed is limited

Engineering Contradiction:
Improvedevice sizeVSAvoidstructure complexity
Core Design Contradiction:
Length of moving objectVSDevice complexity

Solution Approach 1:

The patent transitions from a two-dimensional flat MOSFET structure to a three-dimensional vertically aligned structure. The 2D material stands perpendicular to the substrate, creating a vertical channel that enables further miniaturization while maintaining effective channel length and improving drive speed through enhanced electric field control.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If the contact area between electrodes and 2D material is increased, then connection stability is improved, but contact resistance increases

Engineering Contradiction:
Improveconnection stabilityVSAvoidcontact resistance
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent utilizes the vertical orientation of the 2D material to enable electrode contact at the tip end rather than along the side surface. This vertical contact geometry minimizes the contact area between electrode and 2D material, thereby reducing contact resistance while maintaining reliable electrical connection through direct tip contact.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Length of moving object

If the thickness of 2D material is reduced to several nanometers or less, then device size is reduced, but electron mobility typically decreases

Engineering Contradiction:
Improvematerial thicknessVSAvoidelectron mobility
Core Design Contradiction:
Length of moving objectVSSpeed

Solution Approach 1:

The patent employs transition metal dichalcogenide materials which maintain high electron mobility even when thickness is reduced to several nanometers or less. The specific material selection and vertical alignment configuration preserve the electronic properties necessary for high-speed operation while achieving the required miniaturization.

Inventive Principle:
Principle #35Parameter changes

4Reliability

If a vertically aligned 2D material structure is used, then contact resistance is reduced and electron mobility is maintained, but manufacturing complexity increases

Engineering Contradiction:
Improveelectrical performanceVSAvoidmanufacturing difficulty
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent uses a guide pattern layer formed before the 2D material growth to pre-establish the vertical alignment configuration. This preliminary structuring guides the subsequent chemical vapor deposition process to grow the 2D material in the desired vertical orientation, simplifying the overall manufacturing process despite the complex final structure.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The guide pattern layer acts as an intermediary structure that facilitates the formation of vertically aligned 2D material. This intermediate layer enables controlled vertical growth during chemical vapor deposition and can be removed after the 2D material is formed, making the complex vertical alignment process more manageable.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the creation of transistors with fine sizes and high performance, such as FinFETs with channel widths of 10 nm or less, and gas sensors with high efficiency and reusability, maintaining high electron mobility and surface reactivity.

Implementation Method 1

at least one two-dimensional material capable of adsorbing a desired gas

Methodology Applied
Scientific EffectAdsorption: Adsorption

Implementation Method 2

The heater may be configured to remove the desired gas from being adsorbed onto the two-dimensional material by heating the at least one two-dimensional material

Methodology Applied
Scientific EffectThermal heating: Heating

Implementation Method 3

growing the two-dimensional material on the substrate from a portion of the transition metal layer that is exposed through the trench

Methodology Applied
Scientific EffectChemical vapor deposition: Chemical Vapour Deposition

Data Source

PatentEP3115484B1Device including vertically aligned two-dimensional material and method of forming a vertically aligned two-dimensional material
Publication Date: 2021.07.07 SAMSUNG ELECTRONICS CO LTD
  • EP3115484B1 patent drawingFigure 1
  • EP3115484B1 patent drawingFigure 2~3
  • EP3115484B1 patent drawingFigure 4A~4B

AI summary

A transistor includes a substrate, a two-dimensional material including at least one layer that is substantially vertically aligned on the substrate such that an edge of the layer is on the substrate and the layer extends substantially vertical to the substrate, a source electrode and a drain electrode connected to opposite ends of the two-dimensional material, a gate insulation layer on the two-dimensional material between the source electrode and the drain electrode, and a gate electrode on the gate insulation layer. Each layer includes a semiconductor having a two-dimensional crystal structure.