Vertically Coupled Coil Structures in Semiconductor Passivation
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Solution Overview
Problem
The challenge in semiconductor technology is integrating large passive components, such as analog circuitry components, into sub-micron devices due to their size, which hinders the miniaturization and performance of semiconductor devices.
Innovation Solution
A method for fabricating a circuitry component with two mutually induced coils, where a first coil is formed on a semiconductor substrate, followed by a passivation layer, and a second coil is deposited over the passivation layer, using a process involving metal layer formation, pattern definition, and removal techniques to achieve compact and integrated coil structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If passive components are integrated into sub-micron semiconductor devices, then device functionality is improved, but device size increases
Solution Approach 1:
The patent transitions from planar coil structures to three-dimensional vertically-coupled coil structures. The first and second coils are positioned at different vertical levels separated by a passivation layer, enabling magnetic coupling in the vertical dimension. This dimensional transition allows achieving required inductance values with smaller footprint area, resolving the contradiction between functionality and size.
Solution Approach 2:
The patent implements nested coil structures where the first coil and second coil are vertically coupled through a passivation layer, with each coil potentially containing multiple turns nested within each other. This nesting approach maximizes the use of vertical space, allowing compact integration of passive components without increasing lateral device dimensions.
2Object-generated harmful factors
If coil structures are integrated over passivation layer, then parasitic capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
The passivation layer is formed over the first coil structure before the second coil is created. This preliminary action establishes an electrical isolation barrier that reduces parasitic capacitance between the two coils. The passivation layer is prepared in advance as part of the standard semiconductor fabrication process, making the isolation built-in rather than requiring additional complex steps.
Solution Approach 2:
The patent combines multiple functions into the existing semiconductor fabrication process: the passivation layer simultaneously serves as an electrical isolation layer to reduce parasitic capacitance and as a structural foundation for the vertically-coupled coil architecture. This merging of functions achieves parasitic reduction without proportionally increasing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the integration of compact coil structures, enhancing the performance of semiconductor devices by reducing parasitic capacitance and allowing for more efficient signal processing and transmission, while maintaining the integrity of the semiconductor substrate.
Implementation Method 1
a circuitry component with two mutually induced coils
Data Source
AI summary
A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer.