Vertically Embedded Non-Volatile Memory Emulating NAND Flash
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Solution Overview
Problem
NAND flash memory systems face inefficiencies due to the need for extra programming operations before erase operations and the requirement of erase operations before write operations, leading to prolonged erase and write times, as well as limitations in random bit value changes.
Innovation Solution
A vertically configured non-volatile memory array that interfaces with NAND memory commands, allowing direct write operations without prior erase operations and enabling random access, utilizing a two-terminal cross-point array configuration with mixed valence conductive oxides and electrolytic tunnel barriers, which can be stacked to reduce die size and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an extra programming operation is conducted before erase operation to prevent over-erased cells, then programming reliability is improved, but erase operation time is lengthened
Solution Approach 1:
The patent applies preliminary action by conducting a programming operation before the erase operation to ensure all memory cells are in a known state (logical one). This prevents over-erased cells and programming errors during the subsequent erase operation, directly addressing the reliability improvement while accepting the time cost as necessary for correct operation.
2Reliability
If an erase operation is conducted before write operation in NAND memory, then data integrity is maintained, but write operation time is lengthened
Solution Approach 1:
The patent applies preliminary action by performing an erase operation before the write operation to clear the memory block to a known state (all logical ones). This ensures data integrity by preventing mixing of old and new data, while the time penalty is accepted as necessary for maintaining correct write operations in NAND memory architecture.
3Adaptability or versatility
If NAND memory structure is used to ensure compatibility with standard commands, then system compatibility is improved, but random write capability is limited
Solution Approach 1:
The patent applies segmentation by dividing the memory system into two distinct parts: a NAND flash memory portion that maintains compatibility with standard NAND commands and protocols, and a separate vertically configured non-volatile memory array that enables random write operations. This segmentation allows each part to optimize for its specific function while working together as an integrated system.
Solution Approach 2:
The patent introduces an intermediary layer (the vertically configured non-volatile memory array) that mediates between the host system and the NAND flash memory. This intermediary accepts standard NAND commands for compatibility while providing enhanced random write capability through its own memory architecture, effectively bridging the gap between compatibility requirements and performance needs.
4Speed
If vertically configured non-volatile memory array is used to enable random access and direct writes, then write operation speed is improved, but device complexity increases
Solution Approach 1:
The patent applies dimensionality change by transitioning from a traditional planar (two-dimensional) memory array to a vertically configured (three-dimensional) non-volatile memory array. This vertical stacking enables random access and direct write operations while improving write speed, and the modular stacked architecture can be integrated with existing NAND memory processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces the need for extra operations, enabling faster and more efficient erase and write operations, allowing random bit changes, and decreases power consumption and die size, thereby improving NAND memory system performance and compatibility with existing NAND memory systems.
Implementation Method 1
utilizing a two-terminal cross-point array configuration with mixed valence conductive oxides and electrolytic tunnel barriers
Implementation Method 2
utilizing a two-terminal cross-point array configuration with mixed valence conductive oxides and electrolytic tunnel barriers
Data Source
AI summary
A system and a method for emulating a NAND memory system are disclosed. In the method, a command associated with a NAND memory is received. After receipt of the command, a vertically configured non-volatile memory array is accessed based on the command. In the system, a vertically configured non-volatile memory array is connected with an input/output controller and a memory controller. The memory controller is also connected with the input/output controller. The memory controller is operative to interface with a command associated with a NAND memory and based on the command, to access the vertically configured non-volatile memory array for a data operation, such as a read operation or write operation. An erase operation on the vertically configured non-volatile memory array is not required prior to the write operation. The vertically configured non-volatile memory array can be partitioned into planes, blocks, and sub-planes, for example.