Vertically-Extended Contact for Semiconductor Integration Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor device integration is exacerbated by decreasing process margins in photolithography, making it difficult to achieve highly integrated semiconductor devices with efficient electrical connections and reduced resistance.
Innovation Solution
The semiconductor device design includes a device isolation pattern, impurity regions, and contacts with vertically-extended and horizontally-extended portions, along with nitride patterns and spacers, to enhance contact area and prevent misalignment, thereby reducing electric resistance and improving integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If photolithography process is used for semiconductor device fabrication, then device integration density can be increased, but process margin decreases making it harder to achieve highly integrated devices
Solution Approach 1:
The patent introduces a vertically-extended portion that extends downward from the contact into the device isolation pattern, adding a vertical dimension to the contact structure. This increases the contact area with the impurity region without increasing the horizontal footprint, thereby improving electrical connection reliability while maintaining high integration density
Solution Approach 2:
The vertically-extended portion of the contact is embedded within the device isolation pattern, creating a nested structure where the contact extends into the isolation region. This allows the contact to reach the impurity region more effectively while the isolation pattern provides structural support and electrical isolation
2Reliability
If contact area between impurity region and contact is increased, then electric resistance decreases, but device structure becomes more complex
Solution Approach 1:
The contact structure extends vertically into the device isolation pattern, increasing the contact area with the impurity region through the vertical dimension rather than expanding horizontally. This reduces electric resistance while maintaining a relatively compact horizontal footprint
Solution Approach 2:
The vertically-extended portion is localized specifically at the contact region where electrical connection is needed, while the rest of the device structure maintains its original simplicity. The extension is confined to the necessary area to achieve low resistance without unnecessarily complicating the overall device
Data Source
AI summary
A semiconductor device includes a device isolation pattern on a substrate to define active patterns, a gate electrode crossing the active patterns, first and second impurity regions in each of the active patterns and on both sides of the gate electrode, a bit line crossing the gate electrode, a first contact electrically connecting the first impurity region to the bit line, and a second contact electrically connected to the second impurity region. The second contact includes a vertically-extended portion covering an upper side surface of the second impurity region.