Vertically Offset Bond on Trace Interconnect Structure
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Solution Overview
Problem
Conventional wire-bonding on leadframes requires large interconnect pitches to avoid electrical shorting, limiting the density of bond wire bumps and increasing die size, which hinders the miniaturization of semiconductor devices and increases material costs.
Innovation Solution
The implementation of a vertically offset bond on trace (BOT) interconnect structure on a leadframe, where conductive layers of different heights are formed over lead fingers, allowing bond wire bumps to be positioned closer together without shorting, by overlapping and maintaining sufficient physical separation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional wire-bonding is used on leadframe, then electrical connection is achieved, but large interconnect pitch is required which limits I/O count
Solution Approach 1:
The patent transitions from conventional planar wire-bonding to a three-dimensional vertically offset bond structure. Conductive layers are formed at different heights (first conductive layer at first height, second conductive layer at second height), allowing bond wire bumps to be positioned vertically offset from each other. This dimensional change enables closer horizontal spacing while maintaining electrical isolation, thereby increasing I/O count without compromising connection reliability.
2Quantity of substance
If bond wire bumps are laterally offset to reduce pitch, then I/O count increases, but longer bond fingers are required which increase die size
Solution Approach 1:
Instead of laterally offsetting bond wire bumps which requires longer bond fingers, the patent uses vertical offset to achieve the same pitch reduction. The bond wire bumps are positioned at different heights above the substrate surface, allowing them to be closer horizontally without requiring extended bond finger lengths. This maintains compact die size while achieving high I/O count.
Solution Approach 2:
The patent changes the spatial parameter of bond wire bump positioning from horizontal/lateral arrangement to vertical arrangement. By controlling the height parameter of conductive layers and bond wire bumps, the patent achieves reduced pitch without the penalty of increased bond finger length, thus preventing die size expansion.
3Area of moving object
If smaller die size is achieved, then device footprint is reduced, but interconnect density must be increased to maintain I/O count
Solution Approach 1:
The patent resolves the conflict between small die size and high interconnect density by utilizing the vertical dimension. Multiple conductive layers at different heights allow bond wire bumps to be positioned closer together horizontally without electrical shorting, effectively increasing interconnect density within a compact die area. The vertical stacking of conductive structures enables higher I/O count without proportionally increasing die footprint.
Data Source
AI summary
A semiconductor device has a vertically offset BOT interconnect structure. The vertical offset is achieved with a leadframe having a plurality of lead fingers around a die paddle. A first conductive layer is formed over the lead fingers. A second conductive layer is formed over the lead fingers. Each second conductive layer is positioned adjacent to the first conductive layer and each first conductive layer is positioned adjacent to the second conductive layer. The second conductive layer has a height greater than a height of the first conductive layer. The first and second conductive layers can have a side-by-side arrangement or staggered arrangement. Bumps are formed over the first and second conductive layers. Bond wires are electrically connected to the bumps. A semiconductor die is mounted over the die paddle of the leadframe and electrically connected to the bond wires and BOT interconnect structure.