Vertically Offset Bond On Trace Interconnects for Semiconductor Devices
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Solution Overview
Problem
Semiconductor devices face a challenge in reducing bond wire bump pitch without increasing the length of bond fingers, which is essential for higher interconnect density and smaller device size, while avoiding electrical shorts.
Innovation Solution
The implementation of vertically offset bond on trace (BOT) interconnects formed on recessed and raised bond fingers, allowing for closer placement of bond wire bumps without electrical shorting, achieved through a process involving conductive layers embedded and extended above the substrate surface, with interconnect structures formed over these layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If bond wire bumps are laterally offset between bond fingers to increase interconnect density, then the pitch between bond wire bumps can be reduced, but the bond fingers must be extended in length which consumes die area
Solution Approach 1:
The patent transitions from lateral offset to vertical offset between bond fingers. By stacking bond fingers at different heights (vertical dimension), the design achieves high interconnect density without requiring longer bond fingers in the lateral dimension. This dimensional shift resolves the contradiction by using the vertical axis to achieve density while maintaining compact lateral dimensions.
Solution Approach 2:
The patent implements nested bond fingers where one bond finger is positioned within the vertical projection of another bond finger. This nesting arrangement allows multiple interconnects to occupy overlapping lateral space at different heights, achieving high density without extending the lateral footprint or requiring excessively long bond fingers.
2Quantity of substance
If bond wire bumps are placed closer together to reduce pitch, then interconnect density increases, but electrical shorts between adjacent terminals may occur
Solution Approach 1:
By offsetting bond fingers in the vertical dimension rather than relying solely on lateral separation, the patent achieves electrical isolation through height differences. Bond wire bumps on vertically offset fingers are separated in the Z-direction, preventing electrical shorts even when laterally close, thus maintaining reliability while enabling high density.
Solution Approach 2:
The patent employs asymmetric positioning of bond fingers at different vertical levels rather than symmetric lateral arrangement. This asymmetric vertical stacking creates natural electrical isolation between adjacent terminals while allowing them to be placed closer together laterally, resolving the contradiction between density and electrical isolation.
3Area of stationary object
If device size is reduced to achieve smaller footprint, then power consumption and manufacturing efficiency improve, but interconnect density must be increased to maintain functionality
Solution Approach 1:
The patent uses vertical stacking of bond fingers to achieve high interconnect density within a compact lateral footprint. By utilizing the vertical dimension for interconnect arrangement, the design packs more interconnects into the same die area without requiring lateral expansion, thus reducing overall device footprint while maintaining functionality.
Solution Approach 2:
The nested bond finger configuration allows multiple interconnects to occupy overlapping lateral spaces at different heights. This nesting achieves high interconnect density within a reduced footprint, as the nested arrangement maximizes the use of vertical space rather than requiring proportional lateral expansion.
Data Source
AI summary
A semiconductor device includes a substrate, a first recessed conductive layer embedded and recessed into a first surface of the substrate, and a first raised conductive layer disposed above the first surface. A first vertical offset exists between an upper surface of the first recessed conductive layer and an upper surface of the first raised conductive layer. The device includes a second recessed conductive layer embedded and recessed into a second surface of the substrate. The second surface of the substrate is opposite the first surface. The device includes a second raised conductive layer disposed beneath the second surface and an interconnect structure disposed on the first recessed and raised conductive layers and the second recessed and raised conductive layers. A second vertical offset exists between a lower surface of the second recessed conductive layer and a lower surface of the second recessed conductive layer.