Vertically-Oriented N-Type Transistors for Low-Capacitance Memory Lines
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Solution Overview
Problem
In memory arrays, particularly in DRAM, there is a challenge to minimize parasitic capacitance and cross-talk between data/sense lines while maintaining high conductivity, which affects the performance and signal delivery to individual sense amplifiers.
Innovation Solution
The use of vertically-oriented n-type field effect transistors with conductively-doped semiconductor material for data/sense lines and access lines, along with a conductivity-neutral dopant to restrict the diffusion of dopants like As and P, helps in forming low-resistance, low-capacitance lines that reduce parasitic capacitance and cross-talk.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data/sense lines are made highly conductive to improve signal delivery, then conductivity is improved, but parasitic capacitance and cross-talk between adjacent lines increase
Solution Approach 1:
The patent applies different doping concentrations and types at different locations within the semiconductor structure. Specifically, higher doping concentrations are used in regions where high conductivity is needed for signal delivery, while lower doping concentrations or different dopant types are used in regions where parasitic capacitance must be minimized. This local differentiation of material properties resolves the contradiction between needing high conductivity and avoiding parasitic effects.
Solution Approach 2:
The patent changes physical parameters such as dopant concentration, dopant type, and line geometry to optimize the balance between conductivity and parasitic capacitance. By adjusting these parameters locally along the data/sense lines and in the surrounding semiconductor regions, the patent achieves high signal delivery capability while controlling parasitic effects.
2Stability of the object's composition
If dopant diffusion is allowed to occur during heating to achieve uniform doping, then doping uniformity is improved, but dopant contamination of the channel region increases
Solution Approach 1:
The patent introduces a barrier layer or interface structure that acts as an intermediary between the heavily doped source/drain regions and the channel region. This intermediary structure allows controlled dopant diffusion to achieve uniform doping in the source/drain regions while preventing excessive dopant contamination of the channel region, thus resolving the contradiction between doping uniformity and contamination control.
Solution Approach 2:
The patent segments the semiconductor structure into distinct regions with different doping profiles and introduces intermediate regions that control dopant diffusion. By segmenting the structure and controlling diffusion in each segment separately, the patent achieves uniform doping where needed while preventing contamination in sensitive regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the conductivity of data/sense lines, lowers capacitance, and improves signal delivery to sense amplifiers, leading to better performance and higher integration levels in memory arrays.
Implementation Method 1
The conductivity-neutral dopant restricts diffusion of the at least one of As and P in the silicon-comprising semiconductor material from the first source/drain region location to the channel region location than would otherwise occur under the set of heating conditions in the absence of the conductivity-neutral dopant
Data Source
AI summary
An n-type field effect transistor includes silicon-comprising semiconductor material comprising a pair of source/drain regions having a channel region there-between. At least one of the source/drain regions is conductively doped n-type with at least one of As and P. A conductivity-neutral dopant is in the silicon-comprising semiconductor material in at least one of the channel region and the at least one source/drain region. A gate construction is operatively proximate the channel region. Methods are disclosed.