Vertically Spaced Contact Structures for Low Parasitic Inductance
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Solution Overview
Problem
Conventional power module packages face challenges in achieving high switching velocity with low switching loss due to parasitic inductance from electrically conductive contact structures, which affects the reliability and efficiency of electronic components, particularly in automotive applications.
Innovation Solution
The package design incorporates vertically spaced electrically conductive contact structures with a reliable dielectric decoupling, reducing parasitic inductance by arranging signal and supply pins in parallel and vertically spaced configurations within the encapsulant, thereby minimizing inductance and maintaining electrical integrity during high-speed switching operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional contact structures are used with coplanar arrangement, then manufacturing is simpler, but parasitic inductance increases causing high switching loss
Solution Approach 1:
The patent transitions from a conventional coplanar arrangement of contact structures to a three-dimensional configuration where contact structures are vertically spaced at different heights within the encapsulant. This dimensional change reduces parasitic inductance by minimizing loop area while maintaining manufacturing feasibility through standardized processes.
2Speed
If contact structures are vertically spaced to reduce parasitic inductance, then switching velocity increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the contact structures into separate segments at different vertical levels within the encapsulant. This segmentation allows each contact structure to be positioned and formed independently using standardized manufacturing processes, reducing the overall precision requirements compared to a monolithic structure while achieving the desired vertical spacing for low inductance.
3Object-generated harmful factors
If vertically spaced contact structures are implemented, then parasitic inductance decreases, but device complexity increases
Solution Approach 1:
The patent combines multiple contact structures into a single integrated encapsulated assembly where different contact structures are vertically spaced within the same encapsulant. This merging approach consolidates what would otherwise be separate components into one unit, reducing overall device complexity while maintaining the beneficial vertical spacing for low parasitic inductance.
Data Source
AI summary
A package comprising at least one electronic chip, an encapsulant encapsulating at least part of the at least one electronic chip, a first electrically conductive contact structure extending partially within and partially outside of the encapsulant and being electrically coupled with at least one first terminal of at least one of the at least one electronic chip, and a second electrically conductive contact structure extending partially within and partially outside of the encapsulant and being electrically coupled with at least one second terminal of at least one of the at least one electronic chip, wherein at least a portion of the first electrically conductive contact structure and at least a portion of the second electrically conductive contact structure within the encapsulant are spaced in a direction between two opposing main surfaces of the package.